Merge branches 'clk-amlogic', 'clk-rockchip', 'clk-of', 'clk-freescale' and 'clk-unused' into clk-next

- Replace clk-provider.h with of_clk.h when possible

* clk-amlogic:
  clk: meson: g12a: add MIPI DSI Host Pixel Clock
  dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindings
  clk: meson: enable building as modules
  clk: meson: Kconfig: fix dependency for G12A
  clk: meson: axg: add MIPI DSI Host clock
  clk: meson: axg: add Video Clocks
  dt-bindings: clk: axg-clkc: add MIPI DSI Host clock binding
  dt-bindings: clk: axg-clkc: add Video Clocks

* clk-rockchip:
  clk: rockchip: fix i2s gate bits on rk3066 and rk3188
  clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks
  clk: rockchip: Remove redundant null check before clk_prepare_enable
  clk: rockchip: Add appropriate arch dependencies

* clk-of:
  xtensa: Replace <linux/clk-provider.h> by <linux/of_clk.h>
  sh: boards: Replace <linux/clk-provider.h> by <linux/of_clk.h>

* clk-freescale:
  clk: fsl-flexspi: new driver
  dt-bindings: clock: document the fsl-flexspi-clk device
  clk: divider: add devm_clk_hw_register_divider_table()
  clk: qoriq: provide constants for the type
  clk: fsl-sai: use devm_clk_hw_register_composite_pdata()
  clk: composite: add devm_clk_hw_register_composite_pdata()
  clk: fsl-sai: fix memory leak
  clk: qoriq: Add platform dependencies

* clk-unused:
  clk: scpi: mark scpi_clk_match as maybe unused
  clk: pwm: drop of_match_ptr from of_device_id table

include/dt-bindings/clock/axg-clkc.h

@@ -72,5 +72,30 @@
 #define CLKID_PCIE_CML_EN1			80
 #define CLKID_MIPI_ENABLE			81
 #define CLKID_GEN_CLK				84
+#define CLKID_VPU_0_SEL				92
+#define CLKID_VPU_0				93
+#define CLKID_VPU_1_SEL				95
+#define CLKID_VPU_1				96
+#define CLKID_VPU				97
+#define CLKID_VAPB_0_SEL			99
+#define CLKID_VAPB_0				100
+#define CLKID_VAPB_1_SEL			102
+#define CLKID_VAPB_1				103
+#define CLKID_VAPB_SEL				104
+#define CLKID_VAPB				105
+#define CLKID_VCLK				106
+#define CLKID_VCLK2				107
+#define CLKID_VCLK_DIV1				122
+#define CLKID_VCLK_DIV2				123
+#define CLKID_VCLK_DIV4				124
+#define CLKID_VCLK_DIV6				125
+#define CLKID_VCLK_DIV12			126
+#define CLKID_VCLK2_DIV1			127
+#define CLKID_VCLK2_DIV2			128
+#define CLKID_VCLK2_DIV4			129
+#define CLKID_VCLK2_DIV6			130
+#define CLKID_VCLK2_DIV12			131
+#define CLKID_CTS_ENCL				133
+#define CLKID_VDIN_MEAS				136
 
 #endif /* __AXG_CLKC_H */

include/dt-bindings/clock/fsl,qoriq-clockgen.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+
+#define QORIQ_CLK_SYSCLK	0
+#define QORIQ_CLK_CMUX		1
+#define QORIQ_CLK_HWACCEL	2
+#define QORIQ_CLK_FMAN		3
+#define QORIQ_CLK_PLATFORM_PLL	4
+#define QORIQ_CLK_CORECLK	5
+
+#define QORIQ_CLK_PLL_DIV(x)	((x) - 1)
+
+#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */

include/dt-bindings/clock/g12a-clkc.h

@@ -147,5 +147,7 @@
 #define CLKID_SPICC1_SCLK			261
 #define CLKID_NNA_AXI_CLK			264
 #define CLKID_NNA_CORE_CLK			267
+#define CLKID_MIPI_DSI_PXCLK_SEL		269
+#define CLKID_MIPI_DSI_PXCLK			270
 
 #endif /* __G12A_CLKC_H */