powerpc: Enable PPR save/restore
[PATCH 2/6] powerpc: Enable PPR save/restore SMT thread status register (PPR) is used to set thread priority. This patch enables PPR save/restore feature (CPU_FTR_HAS_PPR) on POWER7 and POWER8 systems. Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -171,6 +171,7 @@ extern const char *powerpc_base_platform;
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#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000)
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#define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000000000000000)
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#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x2000000000000000)
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#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x4000000000000000)
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#ifndef __ASSEMBLY__
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@ -400,7 +401,8 @@ extern const char *powerpc_base_platform;
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
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CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
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CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY)
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CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
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CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR)
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#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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@ -409,7 +411,7 @@ extern const char *powerpc_base_platform;
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CPU_FTR_DSCR | CPU_FTR_SAO | \
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
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CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
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CPU_FTR_DBELL)
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CPU_FTR_DBELL | CPU_FTR_HAS_PPR)
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#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
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