TI K3 device tree updates for v5.18
Since (ti-k3-dt-fixes-for-v5.17): Fixes: * Cleanups for flash nodes across K3. * gic-v3 backward compatible registers * j721s2 interrupt parent fixup for wakeup GPIO New: * AM62 SoC and AM62-SK board * wdt support for am64 -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE+KKGk1TrgjIXoxo03bWEnRc2JJ0FAmIct6oACgkQ3bWEnRc2 JJ0IphAAlXcsR2Eu7QrVn3yD+kQmVGuiiwpSZ4byQ1ZqfzmqCLsmTEAnQuNcEv00 wRiQf//JrdKb81Uho0Ag0a5V9Hwm66aFx80wxhCdZ1oYGq/MbdKOm76GYwJCqQqZ n3TSnRmXYSIdV0T3TfmdmOie+OHosQ+DpICXKC5g5ZMkrQK7t6oS7M/8FJx+UfsE 2FgNzepdPrY241x02CnAPirdL2ptAiCO7qIeLyxCk1yQjXyCsmSLyGDScHnM+6PA E9kO0XA0AeTlrp3U7SzqHAL2rmxXnFP92f1gLC2z3aQ5pwg5kglL/Ll3VwTRBUx9 FfX3sRE1SHLfTTVascgLr8oab/xJ8KR6228Gu/FAOR74i4s0h3kgHppvU3h3HgAe PFm6oWLjQREosb7vmkhMursd3kqkrlg8Kq6dqxAKzcB36QbpkAWlXfpts8g58U2R M3EiYTK81mOVP1V1eUAXu5LdGsTpOFcS7FlYk6l1PbzJPQAkbmSwIgd911kAQsUy Qjj000H3Rv7tH1LluyBR/vm8B3MVrl2PMTAHhi9wV8zaNiqTJWsQO3NgmaPHzYb1 VFGxf+75pdDnq2+DdbyGmvgQSZ1n3fRa/QFvqO62in13R7uwdUpLzWCouLXkdHPu hs2vVo1bzJMVMkihjRKrlkLBjsO6HTKUL2AC9Du8BgAkRwh+aPY= =mVxU -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIc2nEACgkQmmx57+YA GNlIvA/9HiZZ4C42kZ4MgmwysvF1Dx+j5nwhDyFBFmLdlesiy/0LcdanyZhY1vAp kwAmMC4xOnq5o5QAH0F5GuMXYptYk3grJ7rMb4LpQaSeog/74VhRBAzmYafobAqu uongkSBk+ZUXDFwYQ80JZthOKTJcgBKDA0uYj1NQ8GVDKTwFsBoN29XWo5fkVbi7 NBu9vyAjcvhZXW7lUFz9qeoZ1shuQlUBjTfPfL2Fgt8ravNsBttqk382Kg3fd/vN EMsjWfL06iBXayzNfoShrZ2y3ngbxIl9t8QiV8y1Mwzz0KoFZimWjnHvUCR3H55b GVj4Xy6qXAFUZchzd1JeypnT+jHMeJhCSkZkYvDUePFvJxd7i21sdOIjAA8fLERL cR32Nx24Z+4I2Mjq1FGV6RaybUd/zsKITfRoGJj2+iymw7tDnmZnkO8XlQAcvxgq ByBang7hwHYf/5XWm6t+SypBv3Oc7mrj8w34LUVOHz92UXWS0B0LVoVB6j28L5yf NaC3pV0VmH1LT6zobkJP7Ykz0EggjQEmUrWogsEN35B7SNZeAlehGis0qdx+di00 S/Q9eb4a9Wu7dS8q16DaxEf/JNAL0nbpMiRQdwAhyENaN3nAIRaJcLEWOpr6/d7a MxW6wZ578XFqnUppVCm6fbtXUOYBK4A2Y4/2WqX2Zvk8rqRraCQ= =uMlU -----END PGP SIGNATURE----- Merge tag 'ti-k3-dt-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/dt TI K3 device tree updates for v5.18 Since (ti-k3-dt-fixes-for-v5.17): Fixes: * Cleanups for flash nodes across K3. * gic-v3 backward compatible registers * j721s2 interrupt parent fixup for wakeup GPIO New: * AM62 SoC and AM62-SK board * wdt support for am64 * tag 'ti-k3-dt-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: arm64: dts: ti: Add support for AM62-SK arm64: dts: ti: Introduce base support for AM62x SoC dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62 dt-bindings: arm: ti: Add bindings for AM625 SoC arm64: dts: ti: k3-*: Drop address and size cells from flash nodes arm64: dts: ti: k3-*: Fix whitespace around flash@0 nodes arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs arm64: dts: ti: k3-j7200: Fix gic-v3 compatible regs arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regs arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs arm64: dts: ti: k3-j721s2-mcu-wakeup: Fix the interrupt-parent for wkup_gpioX instances arm64: dts: ti: k3-am64: Add ESM0 to device memory map arm64: dts: ti: k3-am65*: Remove #address-cells/#size-cells from flash nodes arm64: dts: ti: k3-am64-main: Add RTI watchdog nodes arm64: dts: ti: k3-j721s2-common-proc-board: Alias console uart to serial2 arm64: dts: ti: k3-j721s2: Move aliases to board dts Link: https://lore.kernel.org/r/20220228120711.xdburehxs5gnwxko@capacity Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
d271758452
@ -46,6 +46,12 @@ properties:
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- ti,j7200-evm
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- const: ti,j7200
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- description: K3 AM625 SoC
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items:
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- enum:
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- ti,am625-sk
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- const: ti,am625
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- description: K3 AM642 SoC
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items:
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- enum:
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@ -21,3 +21,5 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb
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267
arch/arm64/boot/dts/ti/k3-am62-main.dtsi
Normal file
267
arch/arm64/boot/dts/ti/k3-am62-main.dtsi
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@ -0,0 +1,267 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM625 SoC Family Main Domain peripherals
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*
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* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_main {
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01880000 0x00 0xc0000>, /* GICR */
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<0x00 0x01880000 0x00 0xc0000>, /* GICR */
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<0x01 0x00000000 0x00 0x2000>, /* GICC */
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<0x01 0x00010000 0x00 0x1000>, /* GICH */
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<0x01 0x00020000 0x00 0x2000>; /* GICV */
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/*
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* vcpumntirq:
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* virtual CPU interface maintenance interrupt
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*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: msi-controller@1820000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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main_conf: syscon@100000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x00 0x00100000 0x00 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x00100000 0x20000>;
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};
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dmss: bus@48000000 {
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-ranges;
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ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
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ti,sci-dev-id = <25>;
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secure_proxy_main: mailbox@4d000000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x4d000000 0x00 0x80000>,
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<0x00 0x4a600000 0x00 0x80000>,
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<0x00 0x4a400000 0x00 0x80000>;
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interrupt-names = "rx_012";
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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dmsc: system-controller@44043000 {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy_main 12>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x00 0x44043000 0x00 0xfe0>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <2>;
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};
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k3_clks: clock-controller {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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main_pmx0: pinctrl@f4000 {
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compatible = "pinctrl-single";
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reg = <0x00 0xf4000 0x00 0x2ac>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_uart0: serial@2800000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 146 0>;
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clock-names = "fclk";
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};
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main_uart1: serial@2810000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02810000 0x00 0x100>;
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interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 152 0>;
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clock-names = "fclk";
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};
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main_uart2: serial@2820000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02820000 0x00 0x100>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 153 0>;
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clock-names = "fclk";
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};
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main_uart3: serial@2830000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02830000 0x00 0x100>;
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interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 154 0>;
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clock-names = "fclk";
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};
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main_uart4: serial@2840000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02840000 0x00 0x100>;
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interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 155 0>;
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clock-names = "fclk";
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};
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main_uart5: serial@2850000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02850000 0x00 0x100>;
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interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 156 0>;
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clock-names = "fclk";
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};
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main_uart6: serial@2860000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02860000 0x00 0x100>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 158 0>;
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clock-names = "fclk";
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};
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main_i2c0: i2c@20000000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20000000 0x00 0x100>;
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 102 2>;
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clock-names = "fck";
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};
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main_i2c1: i2c@20010000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20010000 0x00 0x100>;
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interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 103 2>;
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clock-names = "fck";
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};
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main_i2c2: i2c@20020000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20020000 0x00 0x100>;
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 104 2>;
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clock-names = "fck";
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};
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main_i2c3: i2c@20030000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20030000 0x00 0x100>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 105 2>;
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clock-names = "fck";
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};
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main_gpio_intr: interrupt-controller@a00000 {
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compatible = "ti,sci-intr";
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reg = <0x00 0x00a00000 0x00 0x800>;
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <3>;
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ti,interrupt-ranges = <0 32 16>;
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};
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main_gpio0: gpio@600000 {
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compatible = "ti,am64-gpio", "ti,keystone-gpio";
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reg = <0x0 0x00600000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&main_gpio_intr>;
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interrupts = <190>, <191>, <192>,
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<193>, <194>, <195>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <87>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 77 0>;
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clock-names = "gpio";
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};
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main_gpio1: gpio@601000 {
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compatible = "ti,am64-gpio", "ti,keystone-gpio";
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reg = <0x0 0x00601000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&main_gpio_intr>;
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interrupts = <180>, <181>, <182>,
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<183>, <184>, <185>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <88>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 78 0>;
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clock-names = "gpio";
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};
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hwspinlock: spinlock@2a000000 {
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compatible = "ti,am64-hwspinlock";
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reg = <0x00 0x2a000000 0x00 0x1000>;
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#hwlock-cells = <1>;
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};
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mailbox0_cluster0: mailbox@29000000 {
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compatible = "ti,am64-mailbox";
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reg = <0x00 0x29000000 0x00 0x200>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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};
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};
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36
arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi
Normal file
36
arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi
Normal file
@ -0,0 +1,36 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM625 SoC Family MCU Domain peripherals
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*
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* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_mcu {
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mcu_pmx0: pinctrl@4084000 {
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compatible = "pinctrl-single";
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reg = <0x00 0x04084000 0x00 0x88>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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mcu_uart0: serial@4a00000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x04a00000 0x00 0x100>;
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interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 149 0>;
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clock-names = "fclk";
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};
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mcu_i2c0: i2c@4900000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x04900000 0x00 0x100>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
|
||||
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 106 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
};
|
||||
41
arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
Normal file
41
arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
Normal file
@ -0,0 +1,41 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM625 SoC Family Wakeup Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_wakeup {
|
||||
wkup_conf: syscon@43000000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x00 0x43000000 0x00 0x20000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x43000000 0x20000>;
|
||||
|
||||
chipid: chipid@14 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x14 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
wkup_uart0: serial@2b300000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x2b300000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 114 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
wkup_i2c0: i2c@2b200000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x02b200000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 107 4>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
};
|
||||
105
arch/arm64/boot/dts/ti/k3-am62.dtsi
Normal file
105
arch/arm64/boot/dts/ti/k3-am62.dtsi
Normal file
@ -0,0 +1,105 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM62 SoC Family
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/k3.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 AM625 SoC";
|
||||
compatible = "ti,am625";
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
chosen { };
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
a53_timer0: timer-cl0-cpu0 {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: bus@f0000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
|
||||
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
|
||||
<0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
|
||||
<0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
|
||||
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
|
||||
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
|
||||
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
|
||||
<0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
|
||||
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
|
||||
<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
|
||||
<0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
|
||||
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
|
||||
<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
|
||||
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
|
||||
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
|
||||
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
|
||||
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
|
||||
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
|
||||
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
|
||||
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
|
||||
|
||||
/* MCU Domain Range */
|
||||
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
|
||||
|
||||
/* Wakeup Domain Range */
|
||||
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
|
||||
|
||||
cbass_mcu: bus@4000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
|
||||
};
|
||||
|
||||
cbass_wakeup: bus@2b000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Now include the peripherals for each bus segments */
|
||||
#include "k3-am62-main.dtsi"
|
||||
#include "k3-am62-mcu.dtsi"
|
||||
#include "k3-am62-wakeup.dtsi"
|
||||
206
arch/arm64/boot/dts/ti/k3-am625-sk.dts
Normal file
206
arch/arm64/boot/dts/ti/k3-am625-sk.dts
Normal file
@ -0,0 +1,206 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* AM625 SK: https://www.ti.com/lit/zip/sprr448
|
||||
*
|
||||
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "k3-am625.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am625-sk", "ti,am625";
|
||||
model = "Texas Instruments AM625 SK";
|
||||
|
||||
aliases {
|
||||
serial2 = &main_uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_tfa_ddr: tfa@9e780000 {
|
||||
reg = <0x00 0x9e780000 0x00 0x80000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9db00000 0x00 0xc00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vmain_pd: regulator-0 {
|
||||
/* TPS65988 PD CONTROLLER OUTPUT */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmain_pd";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_5v0: regulator-1 {
|
||||
/* Output of LM34936 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vmain_pd>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_3v3_sys: regulator-2 {
|
||||
/* output of LM61460-Q1 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_3v3_sys";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vmain_pd>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usr_led_pins_default>;
|
||||
|
||||
led-0 {
|
||||
label = "am62-sk:green:heartbeat";
|
||||
gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
|
||||
AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
|
||||
AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
|
||||
AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
usr_led_pins_default: usr-led-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
/* WKUP UART0 is used by DM firmware */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
/* Main UART1 is used by TIFS firmware */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_uart2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_i2c0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wkup_i2c0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&main_i2c2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
103
arch/arm64/boot/dts/ti/k3-am625.dtsi
Normal file
103
arch/arm64/boot/dts/ti/k3-am625.dtsi
Normal file
@ -0,0 +1,103 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM625 SoC family in Quad core configuration
|
||||
*
|
||||
* TRM: https://www.ti.com/lit/pdf/spruiv7
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am62.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x002>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x003>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-size = <0x40000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
};
|
||||
};
|
||||
@ -59,7 +59,10 @@
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
|
||||
<0x00 0x01840000 0x00 0xC0000>; /* GICR */
|
||||
<0x00 0x01840000 0x00 0xC0000>, /* GICR */
|
||||
<0x01 0x00000000 0x00 0x2000>, /* GICC */
|
||||
<0x01 0x00010000 0x00 0x1000>, /* GICH */
|
||||
<0x01 0x00020000 0x00 0x2000>; /* GICV */
|
||||
/*
|
||||
* vcpumntirq:
|
||||
* virtual CPU interface maintenance interrupt
|
||||
@ -982,6 +985,24 @@
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_rti0: watchdog@e000000 {
|
||||
compatible = "ti,j7-rti-wdt";
|
||||
reg = <0x00 0xe000000 0x00 0x100>;
|
||||
clocks = <&k3_clks 125 0>;
|
||||
power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
|
||||
assigned-clocks = <&k3_clks 125 0>;
|
||||
assigned-clock-parents = <&k3_clks 125 2>;
|
||||
};
|
||||
|
||||
main_rti1: watchdog@e010000 {
|
||||
compatible = "ti,j7-rti-wdt";
|
||||
reg = <0x00 0xe010000 0x00 0x100>;
|
||||
clocks = <&k3_clks 126 0>;
|
||||
power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
|
||||
assigned-clocks = <&k3_clks 126 0>;
|
||||
assigned-clock-parents = <&k3_clks 126 2>;
|
||||
};
|
||||
|
||||
icssg0: icssg@30000000 {
|
||||
compatible = "ti,am642-icssg";
|
||||
reg = <0x00 0x30000000 0x00 0x80000>;
|
||||
|
||||
@ -66,11 +66,14 @@
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
|
||||
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
|
||||
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
|
||||
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
|
||||
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
|
||||
<0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
|
||||
<0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
|
||||
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
|
||||
<0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
|
||||
@ -87,6 +90,7 @@
|
||||
<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
|
||||
<0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
|
||||
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
|
||||
<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
|
||||
|
||||
|
||||
@ -498,7 +498,7 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0{
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
@ -509,8 +509,6 @@
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -369,7 +369,7 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0{
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
@ -380,8 +380,6 @@
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -603,8 +603,6 @@
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -35,7 +35,10 @@
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
|
||||
<0x00 0x01880000 0x00 0x90000>; /* GICR */
|
||||
<0x00 0x01880000 0x00 0x90000>, /* GICR */
|
||||
<0x00 0x6f000000 0x00 0x2000>, /* GICC */
|
||||
<0x00 0x6f010000 0x00 0x1000>, /* GICH */
|
||||
<0x00 0x6f020000 0x00 0x2000>; /* GICV */
|
||||
/*
|
||||
* vcpumntirq:
|
||||
* virtual CPU interface maintenance interrupt
|
||||
|
||||
@ -86,6 +86,7 @@
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
|
||||
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
|
||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
|
||||
|
||||
@ -333,14 +333,12 @@
|
||||
#size-cells= <0>;
|
||||
ti,pindir-d0-out-d1-in;
|
||||
|
||||
flash@0{
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <1>;
|
||||
spi-max-frequency = <48000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells= <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -498,7 +496,7 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
||||
|
||||
flash@0{
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
@ -509,8 +507,6 @@
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -54,7 +54,10 @@
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
|
||||
<0x00 0x01900000 0x00 0x100000>; /* GICR */
|
||||
<0x00 0x01900000 0x00 0x100000>, /* GICR */
|
||||
<0x00 0x6f000000 0x00 0x2000>, /* GICC */
|
||||
<0x00 0x6f010000 0x00 0x1000>, /* GICH */
|
||||
<0x00 0x6f020000 0x00 0x2000>; /* GICV */
|
||||
|
||||
/* vcpumntirq: virtual CPU interface maintenance interrupt */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@ -256,7 +256,7 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
||||
|
||||
flash@0{
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
@ -267,7 +267,5 @@
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -129,6 +129,7 @@
|
||||
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
|
||||
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
|
||||
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
|
||||
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
|
||||
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
|
||||
|
||||
@ -482,7 +482,7 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
|
||||
|
||||
flash@0{
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
@ -493,8 +493,6 @@
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -76,7 +76,10 @@
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
|
||||
<0x00 0x01900000 0x00 0x100000>; /* GICR */
|
||||
<0x00 0x01900000 0x00 0x100000>, /* GICR */
|
||||
<0x00 0x6f000000 0x00 0x2000>, /* GICC */
|
||||
<0x00 0x6f010000 0x00 0x1000>, /* GICH */
|
||||
<0x00 0x6f020000 0x00 0x2000>; /* GICV */
|
||||
|
||||
/* vcpumntirq: virtual CPU interface maintenance interrupt */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@ -475,8 +475,6 @@
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -171,7 +171,7 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
||||
|
||||
flash@0{
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
@ -182,8 +182,6 @@
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -139,6 +139,7 @@
|
||||
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/
|
||||
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
|
||||
<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
|
||||
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
|
||||
<0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
|
||||
<0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
|
||||
<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
|
||||
|
||||
@ -15,8 +15,18 @@
|
||||
model = "Texas Instruments J721S2 EVM";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial10:115200n8";
|
||||
bootargs = "console=ttyS10,115200n8 earlycon=ns16550a,mmio32,2880000";
|
||||
stdout-path = "serial2:115200n8";
|
||||
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,2880000";
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial1 = &mcu_uart0;
|
||||
serial2 = &main_uart8;
|
||||
mmc0 = &main_sdhci0;
|
||||
mmc1 = &main_sdhci1;
|
||||
can0 = &main_mcan16;
|
||||
can1 = &mcu_mcan0;
|
||||
can2 = &mcu_mcan1;
|
||||
};
|
||||
|
||||
evm_12v0: fixedregulator-evm12v0 {
|
||||
|
||||
@ -34,7 +34,10 @@
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
|
||||
<0x00 0x01900000 0x00 0x100000>; /* GICR */
|
||||
<0x00 0x01900000 0x00 0x100000>, /* GICR */
|
||||
<0x00 0x6f000000 0x00 0x2000>, /* GICC */
|
||||
<0x00 0x6f010000 0x00 0x1000>, /* GICH */
|
||||
<0x00 0x6f020000 0x00 0x2000>; /* GICV */
|
||||
|
||||
/* vcpumntirq: virtual CPU interface maintenance interrupt */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@ -108,7 +108,7 @@
|
||||
reg = <0x00 0x42110000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupt-parent = <&wkup_gpio_intr>;
|
||||
interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
@ -124,7 +124,7 @@
|
||||
reg = <0x00 0x42100000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupt-parent = <&wkup_gpio_intr>;
|
||||
interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
@ -21,28 +21,6 @@
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &wkup_uart0;
|
||||
serial1 = &mcu_uart0;
|
||||
serial2 = &main_uart0;
|
||||
serial3 = &main_uart1;
|
||||
serial4 = &main_uart2;
|
||||
serial5 = &main_uart3;
|
||||
serial6 = &main_uart4;
|
||||
serial7 = &main_uart5;
|
||||
serial8 = &main_uart6;
|
||||
serial9 = &main_uart7;
|
||||
serial10 = &main_uart8;
|
||||
serial11 = &main_uart9;
|
||||
mmc0 = &main_sdhci0;
|
||||
mmc1 = &main_sdhci1;
|
||||
can0 = &main_mcan16;
|
||||
can1 = &mcu_mcan0;
|
||||
can2 = &mcu_mcan1;
|
||||
can3 = &main_mcan3;
|
||||
can4 = &main_mcan5;
|
||||
};
|
||||
|
||||
chosen { };
|
||||
|
||||
cpus {
|
||||
@ -141,6 +119,7 @@
|
||||
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
|
||||
<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
|
||||
<0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
|
||||
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
|
||||
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
|
||||
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
|
||||
|
||||
@ -41,4 +41,7 @@
|
||||
#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user