habanalabs: remove ASIC functions of clock gating
Now that clock gating is permanently disabled in GAUDI, no need for the ASIC functions of setting and disabling clock gating, as this was a unique scenario in GAUDI. Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
This commit is contained in:
Oded Gabbay
parent
4edb4ffe39
commit
d280d5954e
@ -644,9 +644,6 @@ int hl_device_set_debug_mode(struct hl_device *hdev, struct hl_ctx *ctx, bool en
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hdev->in_debug = 0;
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if (!hdev->reset_info.hard_reset_pending)
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hdev->asic_funcs->set_clock_gating(hdev);
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goto out;
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}
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@ -657,7 +654,6 @@ int hl_device_set_debug_mode(struct hl_device *hdev, struct hl_ctx *ctx, bool en
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goto out;
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}
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hdev->asic_funcs->disable_clock_gating(hdev);
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hdev->in_debug = 1;
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out:
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@ -1164,9 +1164,6 @@ struct fw_load_mgr {
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* @mmu_invalidate_cache_range: flush specific MMU STLB cache lines with
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* ASID-VA-size mask.
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* @send_heartbeat: send is-alive packet to CPU-CP and verify response.
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* @set_clock_gating: enable/disable clock gating per engine according to
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* clock gating mask in hdev
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* @disable_clock_gating: disable clock gating completely
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* @debug_coresight: perform certain actions on Coresight for debugging.
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* @is_device_idle: return true if device is idle, false otherwise.
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* @non_hard_reset_late_init: perform certain actions needed after a reset which is not hard-reset
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@ -1300,8 +1297,6 @@ struct hl_asic_funcs {
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int (*mmu_invalidate_cache_range)(struct hl_device *hdev, bool is_hard,
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u32 flags, u32 asid, u64 va, u64 size);
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int (*send_heartbeat)(struct hl_device *hdev);
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void (*set_clock_gating)(struct hl_device *hdev);
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void (*disable_clock_gating)(struct hl_device *hdev);
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int (*debug_coresight)(struct hl_device *hdev, struct hl_ctx *ctx, void *data);
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bool (*is_device_idle)(struct hl_device *hdev, u64 *mask_arr,
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u8 mask_len, struct seq_file *s);
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@ -1,7 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2016-2021 HabanaLabs, Ltd.
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* Copyright 2016-2022 HabanaLabs, Ltd.
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* All Rights Reserved.
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*/
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@ -458,7 +458,6 @@ struct ecc_info_extract_params {
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u64 block_address;
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u32 num_memories;
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bool derr;
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bool disable_clock_gating;
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};
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static int gaudi_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
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@ -1896,7 +1895,6 @@ static int gaudi_sw_init(struct hl_device *hdev)
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goto free_cpu_accessible_dma_pool;
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spin_lock_init(&gaudi->hw_queues_lock);
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mutex_init(&gaudi->clk_gate_mutex);
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hdev->supports_sync_stream = true;
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hdev->supports_coresight = true;
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@ -1946,8 +1944,6 @@ static int gaudi_sw_fini(struct hl_device *hdev)
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dma_pool_destroy(hdev->dma_pool);
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mutex_destroy(&gaudi->clk_gate_mutex);
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kfree(gaudi);
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return 0;
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@ -3738,10 +3734,6 @@ static void gaudi_tpc_stall(struct hl_device *hdev)
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WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
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}
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static void gaudi_set_clock_gating(struct hl_device *hdev)
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{
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}
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static void gaudi_disable_clock_gating(struct hl_device *hdev)
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{
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u32 qman_offset;
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@ -3810,8 +3802,6 @@ static void gaudi_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_
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gaudi_stop_hbm_dma_qmans(hdev);
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gaudi_stop_pci_dma_qmans(hdev);
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hdev->asic_funcs->disable_clock_gating(hdev);
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msleep(wait_timeout_ms);
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gaudi_pci_dma_stall(hdev);
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@ -4137,10 +4127,8 @@ static int gaudi_hw_init(struct hl_device *hdev)
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/* In case the clock gating was enabled in preboot we need to disable
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* it here before touching the MME/TPC registers.
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* There is no need to take clk gating mutex because when this function
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* runs, no other relevant code can run
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*/
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hdev->asic_funcs->disable_clock_gating(hdev);
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gaudi_disable_clock_gating(hdev);
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/* SRAM scrambler must be initialized after CPU is running from HBM */
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gaudi_init_scrambler_sram(hdev);
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@ -4166,8 +4154,6 @@ static int gaudi_hw_init(struct hl_device *hdev)
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gaudi_init_nic_qmans(hdev);
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hdev->asic_funcs->set_clock_gating(hdev);
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gaudi_enable_timestamp(hdev);
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/* MSI must be enabled before CPU queues and NIC are initialized */
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@ -4815,7 +4801,6 @@ static int gaudi_hbm_scrubbing(struct hl_device *hdev)
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static int gaudi_scrub_device_mem(struct hl_device *hdev, u64 addr, u64 size)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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struct gaudi_device *gaudi = hdev->asic_specific;
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int rc = 0;
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u64 val = 0;
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@ -4850,17 +4835,11 @@ static int gaudi_scrub_device_mem(struct hl_device *hdev, u64 addr, u64 size)
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return rc;
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}
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mutex_lock(&gaudi->clk_gate_mutex);
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hdev->asic_funcs->disable_clock_gating(hdev);
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/* Scrub HBM using all DMA channels in parallel */
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rc = gaudi_hbm_scrubbing(hdev);
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if (rc)
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dev_err(hdev->dev,
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"Failed to clear HBM in mem scrub all\n");
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hdev->asic_funcs->set_clock_gating(hdev);
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mutex_unlock(&gaudi->clk_gate_mutex);
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}
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return rc;
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@ -6344,7 +6323,6 @@ static int gaudi_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size,
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void *blob_addr)
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{
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u32 dma_core_sts0, err_cause, cfg1, size_left, pos, size_to_dma;
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struct gaudi_device *gaudi = hdev->asic_specific;
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u32 qm_glbl_sts0, qm_cgm_sts;
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u64 dma_offset, qm_offset;
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dma_addr_t dma_addr;
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@ -6360,10 +6338,6 @@ static int gaudi_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size,
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if (!kernel_addr)
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return -ENOMEM;
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mutex_lock(&gaudi->clk_gate_mutex);
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hdev->asic_funcs->disable_clock_gating(hdev);
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hdev->asic_funcs->hw_queues_lock(hdev);
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dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_1];
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@ -6448,10 +6422,6 @@ static int gaudi_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size,
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out:
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hdev->asic_funcs->hw_queues_unlock(hdev);
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hdev->asic_funcs->set_clock_gating(hdev);
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mutex_unlock(&gaudi->clk_gate_mutex);
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hdev->asic_funcs->asic_dma_free_coherent(hdev, SZ_2M, kernel_addr,
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dma_addr);
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@ -6499,10 +6469,6 @@ static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid)
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return;
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}
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mutex_lock(&gaudi->clk_gate_mutex);
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hdev->asic_funcs->disable_clock_gating(hdev);
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gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_0, asid);
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gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_1, asid);
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gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_2, asid);
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@ -6780,10 +6746,6 @@ static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid)
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gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_ARUSER, asid);
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gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_AWUSER, asid);
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hdev->asic_funcs->set_clock_gating(hdev);
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mutex_unlock(&gaudi->clk_gate_mutex);
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}
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static int gaudi_send_job_on_qman0(struct hl_device *hdev,
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@ -7164,10 +7126,8 @@ static int gaudi_extract_ecc_info(struct hl_device *hdev,
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struct ecc_info_extract_params *params, u64 *ecc_address,
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u64 *ecc_syndrom, u8 *memory_wrapper_idx)
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{
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struct gaudi_device *gaudi = hdev->asic_specific;
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u32 i, num_mem_regs, reg, err_bit;
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u64 err_addr, err_word = 0;
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int rc = 0;
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num_mem_regs = params->num_memories / 32 +
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((params->num_memories % 32) ? 1 : 0);
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@ -7180,11 +7140,6 @@ static int gaudi_extract_ecc_info(struct hl_device *hdev,
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else
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err_addr = params->block_address + GAUDI_ECC_SERR0_OFFSET;
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if (params->disable_clock_gating) {
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mutex_lock(&gaudi->clk_gate_mutex);
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hdev->asic_funcs->disable_clock_gating(hdev);
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}
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/* Set invalid wrapper index */
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*memory_wrapper_idx = 0xFF;
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@ -7201,8 +7156,7 @@ static int gaudi_extract_ecc_info(struct hl_device *hdev,
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if (*memory_wrapper_idx == 0xFF) {
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dev_err(hdev->dev, "ECC error information cannot be found\n");
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rc = -EINVAL;
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goto enable_clk_gate;
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return -EINVAL;
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}
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WREG32(params->block_address + GAUDI_ECC_MEM_SEL_OFFSET,
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@ -7222,14 +7176,7 @@ static int gaudi_extract_ecc_info(struct hl_device *hdev,
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WREG32(params->block_address + GAUDI_ECC_MEM_INFO_CLR_OFFSET, reg);
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enable_clk_gate:
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if (params->disable_clock_gating) {
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hdev->asic_funcs->set_clock_gating(hdev);
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mutex_unlock(&gaudi->clk_gate_mutex);
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}
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return rc;
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return 0;
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}
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/*
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@ -7487,7 +7434,6 @@ static void gaudi_handle_ecc_event(struct hl_device *hdev, u16 event_type,
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params.block_address = mmTPC0_CFG_BASE + index * TPC_CFG_OFFSET;
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params.num_memories = 90;
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params.derr = false;
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params.disable_clock_gating = true;
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extract_info_from_fw = false;
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break;
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case GAUDI_EVENT_TPC0_DERR ... GAUDI_EVENT_TPC7_DERR:
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@ -7496,7 +7442,6 @@ static void gaudi_handle_ecc_event(struct hl_device *hdev, u16 event_type,
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mmTPC0_CFG_BASE + index * TPC_CFG_OFFSET;
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params.num_memories = 90;
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params.derr = true;
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params.disable_clock_gating = true;
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extract_info_from_fw = false;
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break;
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case GAUDI_EVENT_MME0_ACC_SERR:
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@ -7507,7 +7452,6 @@ static void gaudi_handle_ecc_event(struct hl_device *hdev, u16 event_type,
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params.block_address = mmMME0_ACC_BASE + index * MME_ACC_OFFSET;
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params.num_memories = 128;
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params.derr = false;
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params.disable_clock_gating = true;
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extract_info_from_fw = false;
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break;
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case GAUDI_EVENT_MME0_ACC_DERR:
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@ -7518,7 +7462,6 @@ static void gaudi_handle_ecc_event(struct hl_device *hdev, u16 event_type,
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params.block_address = mmMME0_ACC_BASE + index * MME_ACC_OFFSET;
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params.num_memories = 128;
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params.derr = true;
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params.disable_clock_gating = true;
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extract_info_from_fw = false;
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break;
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case GAUDI_EVENT_MME0_SBAB_SERR:
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@ -7530,7 +7473,6 @@ static void gaudi_handle_ecc_event(struct hl_device *hdev, u16 event_type,
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mmMME0_SBAB_BASE + index * MME_ACC_OFFSET;
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params.num_memories = 33;
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params.derr = false;
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params.disable_clock_gating = true;
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extract_info_from_fw = false;
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break;
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case GAUDI_EVENT_MME0_SBAB_DERR:
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@ -7542,7 +7484,6 @@ static void gaudi_handle_ecc_event(struct hl_device *hdev, u16 event_type,
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mmMME0_SBAB_BASE + index * MME_ACC_OFFSET;
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params.num_memories = 33;
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params.derr = true;
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params.disable_clock_gating = true;
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extract_info_from_fw = false;
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break;
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default:
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@ -7864,19 +7805,9 @@ static int gaudi_hbm_event_to_dev(u16 hbm_event_type)
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static bool gaudi_tpc_read_interrupts(struct hl_device *hdev, u8 tpc_id,
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char *interrupt_name)
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{
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struct gaudi_device *gaudi = hdev->asic_specific;
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u32 tpc_offset = tpc_id * TPC_CFG_OFFSET, tpc_interrupts_cause, i;
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bool soft_reset_required = false;
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/* Accessing the TPC_INTR_CAUSE registers requires disabling the clock
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* gating, and thus cannot be done in CPU-CP and should be done instead
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* by the driver.
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*/
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mutex_lock(&gaudi->clk_gate_mutex);
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hdev->asic_funcs->disable_clock_gating(hdev);
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tpc_interrupts_cause = RREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset) &
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TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK;
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@ -7894,10 +7825,6 @@ static bool gaudi_tpc_read_interrupts(struct hl_device *hdev, u8 tpc_id,
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/* Clear interrupts */
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WREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset, 0);
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hdev->asic_funcs->set_clock_gating(hdev);
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mutex_unlock(&gaudi->clk_gate_mutex);
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return soft_reset_required;
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}
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@ -8359,10 +8286,6 @@ static bool gaudi_is_device_idle(struct hl_device *hdev, u64 *mask_arr,
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u64 offset;
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int i, dma_id, port;
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mutex_lock(&gaudi->clk_gate_mutex);
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hdev->asic_funcs->disable_clock_gating(hdev);
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if (s)
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seq_puts(s,
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"\nDMA is_idle QM_GLBL_STS0 QM_CGM_STS DMA_CORE_STS0\n"
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@ -8483,10 +8406,6 @@ static bool gaudi_is_device_idle(struct hl_device *hdev, u64 *mask_arr,
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if (s)
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seq_puts(s, "\n");
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hdev->asic_funcs->set_clock_gating(hdev);
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mutex_unlock(&gaudi->clk_gate_mutex);
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return is_idle;
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}
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@ -8526,10 +8445,8 @@ static int gaudi_get_eeprom_data(struct hl_device *hdev, void *data,
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* this function should be used only during initialization and/or after reset,
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* when there are no active users.
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*/
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static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel,
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u32 tpc_id)
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static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel, u32 tpc_id)
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{
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struct gaudi_device *gaudi = hdev->asic_specific;
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u64 kernel_timeout;
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u32 status, offset;
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int rc;
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@ -8541,10 +8458,6 @@ static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel,
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else
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kernel_timeout = HL_DEVICE_TIMEOUT_USEC;
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mutex_lock(&gaudi->clk_gate_mutex);
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hdev->asic_funcs->disable_clock_gating(hdev);
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WREG32(mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW + offset,
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lower_32_bits(tpc_kernel));
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WREG32(mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH + offset,
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@ -8584,8 +8497,6 @@ static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel,
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dev_err(hdev->dev,
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"Timeout while waiting for TPC%d icache prefetch\n",
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tpc_id);
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hdev->asic_funcs->set_clock_gating(hdev);
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mutex_unlock(&gaudi->clk_gate_mutex);
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return -EIO;
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}
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@ -8609,8 +8520,6 @@ static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel,
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dev_err(hdev->dev,
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"Timeout while waiting for TPC%d vector pipe\n",
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tpc_id);
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hdev->asic_funcs->set_clock_gating(hdev);
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mutex_unlock(&gaudi->clk_gate_mutex);
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return -EIO;
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}
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@ -8622,9 +8531,6 @@ static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel,
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1000,
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kernel_timeout);
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hdev->asic_funcs->set_clock_gating(hdev);
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mutex_unlock(&gaudi->clk_gate_mutex);
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if (rc) {
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dev_err(hdev->dev,
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"Timeout while waiting for TPC%d kernel to execute\n",
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@ -9191,23 +9097,15 @@ static int gaudi_gen_sync_to_engine_map(struct hl_device *hdev,
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||||
struct hl_sync_to_engine_map *map)
|
||||
{
|
||||
struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
|
||||
struct gaudi_device *gaudi = hdev->asic_specific;
|
||||
int i, j, rc;
|
||||
u32 reg_value;
|
||||
|
||||
/* Iterate over TPC engines */
|
||||
for (i = 0; i < sds->props[SP_NUM_OF_TPC_ENGINES]; ++i) {
|
||||
/* TPC registered must be accessed with clock gating disabled */
|
||||
mutex_lock(&gaudi->clk_gate_mutex);
|
||||
hdev->asic_funcs->disable_clock_gating(hdev);
|
||||
|
||||
reg_value = RREG32(sds->props[SP_TPC0_CFG_SO] +
|
||||
sds->props[SP_NEXT_TPC] * i);
|
||||
|
||||
/* We can reenable clock_gating */
|
||||
hdev->asic_funcs->set_clock_gating(hdev);
|
||||
mutex_unlock(&gaudi->clk_gate_mutex);
|
||||
|
||||
rc = gaudi_add_sync_to_engine_map_entry(map, reg_value,
|
||||
ENGINE_TPC, i);
|
||||
if (rc)
|
||||
@ -9217,20 +9115,11 @@ static int gaudi_gen_sync_to_engine_map(struct hl_device *hdev,
|
||||
/* Iterate over MME engines */
|
||||
for (i = 0; i < sds->props[SP_NUM_OF_MME_ENGINES]; ++i) {
|
||||
for (j = 0; j < sds->props[SP_SUB_MME_ENG_NUM]; ++j) {
|
||||
/* MME registered must be accessed with clock gating
|
||||
* disabled
|
||||
*/
|
||||
mutex_lock(&gaudi->clk_gate_mutex);
|
||||
hdev->asic_funcs->disable_clock_gating(hdev);
|
||||
|
||||
reg_value = RREG32(sds->props[SP_MME_CFG_SO] +
|
||||
sds->props[SP_NEXT_MME] * i +
|
||||
j * sizeof(u32));
|
||||
|
||||
/* We can reenable clock_gating */
|
||||
hdev->asic_funcs->set_clock_gating(hdev);
|
||||
mutex_unlock(&gaudi->clk_gate_mutex);
|
||||
|
||||
rc = gaudi_add_sync_to_engine_map_entry(
|
||||
map, reg_value, ENGINE_MME,
|
||||
i * sds->props[SP_SUB_MME_ENG_NUM] + j);
|
||||
@ -9481,8 +9370,6 @@ static const struct hl_asic_funcs gaudi_funcs = {
|
||||
.mmu_invalidate_cache = gaudi_mmu_invalidate_cache,
|
||||
.mmu_invalidate_cache_range = gaudi_mmu_invalidate_cache_range,
|
||||
.send_heartbeat = gaudi_send_heartbeat,
|
||||
.set_clock_gating = gaudi_set_clock_gating,
|
||||
.disable_clock_gating = gaudi_disable_clock_gating,
|
||||
.debug_coresight = gaudi_debug_coresight,
|
||||
.is_device_idle = gaudi_is_device_idle,
|
||||
.non_hard_reset_late_init = gaudi_non_hard_reset_late_init,
|
||||
|
||||
@ -312,8 +312,6 @@ struct gaudi_internal_qman_info {
|
||||
* struct gaudi_device - ASIC specific manage structure.
|
||||
* @cpucp_info_get: get information on device from CPU-CP
|
||||
* @hw_queues_lock: protects the H/W queues from concurrent access.
|
||||
* @clk_gate_mutex: protects code areas that require clock gating to be disabled
|
||||
* temporarily
|
||||
* @internal_qmans: Internal QMANs information. The array size is larger than
|
||||
* the actual number of internal queues because they are not in
|
||||
* consecutive order.
|
||||
@ -336,7 +334,6 @@ struct gaudi_device {
|
||||
|
||||
/* TODO: remove hw_queues_lock after moving to scheduler code */
|
||||
spinlock_t hw_queues_lock;
|
||||
struct mutex clk_gate_mutex;
|
||||
|
||||
struct gaudi_internal_qman_info internal_qmans[GAUDI_QUEUE_ID_SIZE];
|
||||
|
||||
|
||||
@ -5391,16 +5391,6 @@ int goya_cpucp_info_get(struct hl_device *hdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void goya_set_clock_gating(struct hl_device *hdev)
|
||||
{
|
||||
/* clock gating not supported in Goya */
|
||||
}
|
||||
|
||||
static void goya_disable_clock_gating(struct hl_device *hdev)
|
||||
{
|
||||
/* clock gating not supported in Goya */
|
||||
}
|
||||
|
||||
static bool goya_is_device_idle(struct hl_device *hdev, u64 *mask_arr,
|
||||
u8 mask_len, struct seq_file *s)
|
||||
{
|
||||
@ -5734,8 +5724,6 @@ static const struct hl_asic_funcs goya_funcs = {
|
||||
.mmu_invalidate_cache = goya_mmu_invalidate_cache,
|
||||
.mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range,
|
||||
.send_heartbeat = goya_send_heartbeat,
|
||||
.set_clock_gating = goya_set_clock_gating,
|
||||
.disable_clock_gating = goya_disable_clock_gating,
|
||||
.debug_coresight = goya_debug_coresight,
|
||||
.is_device_idle = goya_is_device_idle,
|
||||
.non_hard_reset_late_init = goya_non_hard_reset_late_init,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user