[ARM] pxa: define SSP platform devices for pxa2xx/pxa3xx
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -13,4 +13,12 @@ extern struct platform_device pxa_device_rtc;
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extern struct platform_device pxa27x_device_i2c_power;
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extern struct platform_device pxa27x_device_ohci;
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extern struct platform_device pxa25x_device_ssp;
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extern struct platform_device pxa25x_device_nssp;
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extern struct platform_device pxa25x_device_assp;
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extern struct platform_device pxa27x_device_ssp1;
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extern struct platform_device pxa27x_device_ssp2;
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extern struct platform_device pxa27x_device_ssp3;
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extern struct platform_device pxa3xx_device_ssp4;
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void __init pxa_register_device(struct platform_device *dev, void *data);
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@ -24,6 +24,7 @@
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#include <linux/ioport.h>
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#include <linux/pm.h>
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#include <linux/string.h>
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#include <linux/dma-mapping.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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@ -487,3 +488,279 @@ struct platform_device pxa_device_rtc = {
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.name = "sa1100-rtc",
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.id = -1,
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};
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#ifdef CONFIG_PXA25x
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static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
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static struct resource pxa25x_resource_ssp[] = {
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[0] = {
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.start = 0x41000000,
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.end = 0x4100001f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_SSP,
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.end = IRQ_SSP,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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/* DRCMR for RX */
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.start = 13,
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.end = 13,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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/* DRCMR for TX */
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.start = 14,
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.end = 14,
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.flags = IORESOURCE_DMA,
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},
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};
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struct platform_device pxa25x_device_ssp = {
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.name = "pxa25x-ssp",
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.id = 0,
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.dev = {
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.dma_mask = &pxa25x_ssp_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.resource = pxa25x_resource_ssp,
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.num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
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};
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static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
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static struct resource pxa25x_resource_nssp[] = {
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[0] = {
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.start = 0x41400000,
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.end = 0x4140002f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_NSSP,
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.end = IRQ_NSSP,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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/* DRCMR for RX */
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.start = 15,
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.end = 15,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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/* DRCMR for TX */
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.start = 16,
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.end = 16,
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.flags = IORESOURCE_DMA,
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},
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};
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struct platform_device pxa25x_device_nssp = {
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.name = "pxa25x-nssp",
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.id = 1,
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.dev = {
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.dma_mask = &pxa25x_nssp_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.resource = pxa25x_resource_nssp,
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.num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
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};
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static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
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static struct resource pxa25x_resource_assp[] = {
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[0] = {
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.start = 0x41500000,
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.end = 0x4150002f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_ASSP,
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.end = IRQ_ASSP,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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/* DRCMR for RX */
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.start = 23,
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.end = 23,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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/* DRCMR for TX */
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.start = 24,
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.end = 24,
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.flags = IORESOURCE_DMA,
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},
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};
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struct platform_device pxa25x_device_assp = {
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/* ASSP is basically equivalent to NSSP */
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.name = "pxa25x-nssp",
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.id = 2,
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.dev = {
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.dma_mask = &pxa25x_assp_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.resource = pxa25x_resource_assp,
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.num_resources = ARRAY_SIZE(pxa25x_resource_assp),
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};
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#endif /* CONFIG_PXA25x */
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#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
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static struct resource pxa27x_resource_ssp1[] = {
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[0] = {
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.start = 0x41000000,
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.end = 0x4100003f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_SSP,
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.end = IRQ_SSP,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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/* DRCMR for RX */
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.start = 13,
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.end = 13,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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/* DRCMR for TX */
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.start = 14,
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.end = 14,
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.flags = IORESOURCE_DMA,
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},
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};
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struct platform_device pxa27x_device_ssp1 = {
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.name = "pxa27x-ssp",
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.id = 0,
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.dev = {
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.dma_mask = &pxa27x_ssp1_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.resource = pxa27x_resource_ssp1,
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.num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
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};
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static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
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static struct resource pxa27x_resource_ssp2[] = {
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[0] = {
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.start = 0x41700000,
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.end = 0x4170003f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_SSP2,
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.end = IRQ_SSP2,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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/* DRCMR for RX */
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.start = 15,
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.end = 15,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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/* DRCMR for TX */
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.start = 16,
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.end = 16,
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.flags = IORESOURCE_DMA,
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},
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};
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struct platform_device pxa27x_device_ssp2 = {
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.name = "pxa27x-ssp",
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.id = 1,
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.dev = {
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.dma_mask = &pxa27x_ssp2_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.resource = pxa27x_resource_ssp2,
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.num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
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};
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static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
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static struct resource pxa27x_resource_ssp3[] = {
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[0] = {
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.start = 0x41900000,
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.end = 0x4190003f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_SSP3,
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.end = IRQ_SSP3,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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/* DRCMR for RX */
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.start = 66,
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.end = 66,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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/* DRCMR for TX */
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.start = 67,
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.end = 67,
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.flags = IORESOURCE_DMA,
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},
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};
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struct platform_device pxa27x_device_ssp3 = {
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.name = "pxa27x-ssp",
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.id = 2,
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.dev = {
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.dma_mask = &pxa27x_ssp3_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.resource = pxa27x_resource_ssp3,
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.num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
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};
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#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
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#ifdef CONFIG_PXA3xx
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static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
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static struct resource pxa3xx_resource_ssp4[] = {
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[0] = {
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.start = 0x41a00000,
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.end = 0x41a0003f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_SSP4,
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.end = IRQ_SSP4,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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/* DRCMR for RX */
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.start = 2,
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.end = 2,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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/* DRCMR for TX */
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.start = 3,
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.end = 3,
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.flags = IORESOURCE_DMA,
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},
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};
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struct platform_device pxa3xx_device_ssp4 = {
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/* PXA3xx SSP is basically equivalent to PXA27x */
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.name = "pxa27x-ssp",
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.id = 3,
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.dev = {
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.dma_mask = &pxa3xx_ssp4_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.resource = pxa3xx_resource_ssp4,
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.num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
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};
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#endif /* CONFIG_PXA3xx */
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