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drm/amd/display: Connect dig_fe to otg directly instead of calling bios

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[Why] After call bios table crtc_source_select, dal will program fmt
again. The bios table program dig_source_select and other fmt register
for bios usage which is redundancy and uncessary.

[How] Program dig_soruce_select register directly

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
hersen wu 2019-01-11 12:43:20 -05:00 committed by Alex Deucher
parent 0f74e48491
commit d2c460e753
13 changed files with 39 additions and 280 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
View File

@ -835,18 +835,6 @@ static enum bp_result bios_parser_enable_crtc(
return bp->cmd_tbl.enable_crtc(bp, id, enable); return bp->cmd_tbl.enable_crtc(bp, id, enable);
} }
static enum bp_result bios_parser_crtc_source_select(
struct dc_bios *dcb,
struct bp_crtc_source_select *bp_params)
{
struct bios_parser *bp = BP_FROM_DCB(dcb);
if (!bp->cmd_tbl.select_crtc_source)
return BP_RESULT_FAILURE;
return bp->cmd_tbl.select_crtc_source(bp, bp_params);
}
static enum bp_result bios_parser_enable_disp_power_gating( static enum bp_result bios_parser_enable_disp_power_gating(
struct dc_bios *dcb, struct dc_bios *dcb,
enum controller_id controller_id, enum controller_id controller_id,
@ -2842,8 +2830,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
.program_crtc_timing = bios_parser_program_crtc_timing, /* still use. should probably retire and program directly */ .program_crtc_timing = bios_parser_program_crtc_timing, /* still use. should probably retire and program directly */
.crtc_source_select = bios_parser_crtc_source_select, /* still use. should probably retire and program directly */
.program_display_engine_pll = bios_parser_program_display_engine_pll, .program_display_engine_pll = bios_parser_program_display_engine_pll,
.enable_disp_power_gating = bios_parser_enable_disp_power_gating, .enable_disp_power_gating = bios_parser_enable_disp_power_gating,

14
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
View File

@ -1083,18 +1083,6 @@ static enum bp_result bios_parser_enable_crtc(
return bp->cmd_tbl.enable_crtc(bp, id, enable); return bp->cmd_tbl.enable_crtc(bp, id, enable);
} }
static enum bp_result bios_parser_crtc_source_select(
struct dc_bios *dcb,
struct bp_crtc_source_select *bp_params)
{
struct bios_parser *bp = BP_FROM_DCB(dcb);
if (!bp->cmd_tbl.select_crtc_source)
return BP_RESULT_FAILURE;
return bp->cmd_tbl.select_crtc_source(bp, bp_params);
}
static enum bp_result bios_parser_enable_disp_power_gating( static enum bp_result bios_parser_enable_disp_power_gating(
struct dc_bios *dcb, struct dc_bios *dcb,
enum controller_id controller_id, enum controller_id controller_id,
@ -1915,8 +1903,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
.program_crtc_timing = bios_parser_program_crtc_timing, .program_crtc_timing = bios_parser_program_crtc_timing,
.crtc_source_select = bios_parser_crtc_source_select,
.enable_disp_power_gating = bios_parser_enable_disp_power_gating, .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
.bios_parser_destroy = firmware_parser_destroy, .bios_parser_destroy = firmware_parser_destroy,

116
drivers/gpu/drm/amd/display/dc/bios/command_table.c
View File

@ -55,7 +55,6 @@ static void init_adjust_display_pll(struct bios_parser *bp);
static void init_dac_encoder_control(struct bios_parser *bp); static void init_dac_encoder_control(struct bios_parser *bp);
static void init_dac_output_control(struct bios_parser *bp); static void init_dac_output_control(struct bios_parser *bp);
static void init_set_crtc_timing(struct bios_parser *bp); static void init_set_crtc_timing(struct bios_parser *bp);
static void init_select_crtc_source(struct bios_parser *bp);
static void init_enable_crtc(struct bios_parser *bp); static void init_enable_crtc(struct bios_parser *bp);
static void init_enable_crtc_mem_req(struct bios_parser *bp); static void init_enable_crtc_mem_req(struct bios_parser *bp);
static void init_external_encoder_control(struct bios_parser *bp); static void init_external_encoder_control(struct bios_parser *bp);
@ -73,7 +72,6 @@ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
init_dac_encoder_control(bp); init_dac_encoder_control(bp);
init_dac_output_control(bp); init_dac_output_control(bp);
init_set_crtc_timing(bp); init_set_crtc_timing(bp);
init_select_crtc_source(bp);
init_enable_crtc(bp); init_enable_crtc(bp);
init_enable_crtc_mem_req(bp); init_enable_crtc_mem_req(bp);
init_program_clock(bp); init_program_clock(bp);
@ -1895,120 +1893,6 @@ static enum bp_result set_crtc_using_dtd_timing_v3(
return result; return result;
} }
/*******************************************************************************
********************************************************************************
**
** SELECT CRTC SOURCE
**
********************************************************************************
*******************************************************************************/
static enum bp_result select_crtc_source_v2(
struct bios_parser *bp,
struct bp_crtc_source_select *bp_params);
static enum bp_result select_crtc_source_v3(
struct bios_parser *bp,
struct bp_crtc_source_select *bp_params);
static void init_select_crtc_source(struct bios_parser *bp)
{
switch (BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source)) {
case 2:
bp->cmd_tbl.select_crtc_source = select_crtc_source_v2;
break;
case 3:
bp->cmd_tbl.select_crtc_source = select_crtc_source_v3;
break;
default:
dm_output_to_console("Don't select_crtc_source enable_crtc for v%d\n",
BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source));
bp->cmd_tbl.select_crtc_source = NULL;
break;
}
}
static enum bp_result select_crtc_source_v2(
struct bios_parser *bp,
struct bp_crtc_source_select *bp_params)
{
enum bp_result result = BP_RESULT_FAILURE;
SELECT_CRTC_SOURCE_PARAMETERS_V2 params;
uint8_t atom_controller_id;
uint32_t atom_engine_id;
enum signal_type s = bp_params->signal;
memset(&params, 0, sizeof(params));
/* set controller id */
if (bp->cmd_helper->controller_id_to_atom(
bp_params->controller_id, &atom_controller_id))
params.ucCRTC = atom_controller_id;
else
return BP_RESULT_FAILURE;
/* set encoder id */
if (bp->cmd_helper->engine_bp_to_atom(
bp_params->engine_id, &atom_engine_id))
params.ucEncoderID = (uint8_t)atom_engine_id;
else
return BP_RESULT_FAILURE;
if (SIGNAL_TYPE_EDP == s ||
(SIGNAL_TYPE_DISPLAY_PORT == s &&
SIGNAL_TYPE_LVDS == bp_params->sink_signal))
s = SIGNAL_TYPE_LVDS;
params.ucEncodeMode =
(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
s, bp_params->enable_dp_audio);
if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
result = BP_RESULT_OK;
return result;
}
static enum bp_result select_crtc_source_v3(
struct bios_parser *bp,
struct bp_crtc_source_select *bp_params)
{
bool result = BP_RESULT_FAILURE;
SELECT_CRTC_SOURCE_PARAMETERS_V3 params;
uint8_t atom_controller_id;
uint32_t atom_engine_id;
enum signal_type s = bp_params->signal;
memset(&params, 0, sizeof(params));
if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
&atom_controller_id))
params.ucCRTC = atom_controller_id;
else
return result;
if (bp->cmd_helper->engine_bp_to_atom(bp_params->engine_id,
&atom_engine_id))
params.ucEncoderID = (uint8_t)atom_engine_id;
else
return result;
if (SIGNAL_TYPE_EDP == s ||
(SIGNAL_TYPE_DISPLAY_PORT == s &&
SIGNAL_TYPE_LVDS == bp_params->sink_signal))
s = SIGNAL_TYPE_LVDS;
params.ucEncodeMode =
bp->cmd_helper->encoder_mode_bp_to_atom(
s, bp_params->enable_dp_audio);
/* Needed for VBIOS Random Spatial Dithering feature */
params.ucDstBpc = (uint8_t)(bp_params->display_output_bit_depth);
if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
result = BP_RESULT_OK;
return result;
}
/******************************************************************************* /*******************************************************************************
******************************************************************************** ********************************************************************************
** **

3
drivers/gpu/drm/amd/display/dc/bios/command_table.h
View File

@ -71,9 +71,6 @@ struct cmd_tbl {
enum bp_result (*set_crtc_timing)( enum bp_result (*set_crtc_timing)(
struct bios_parser *bp, struct bios_parser *bp,
struct bp_hw_crtc_timing_parameters *bp_params); struct bp_hw_crtc_timing_parameters *bp_params);
enum bp_result (*select_crtc_source)(
struct bios_parser *bp,
struct bp_crtc_source_select *bp_params);
enum bp_result (*enable_crtc)( enum bp_result (*enable_crtc)(
struct bios_parser *bp, struct bios_parser *bp,
enum controller_id controller_id, enum controller_id controller_id,

70
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
View File

@ -460,75 +460,6 @@ static enum bp_result set_crtc_using_dtd_timing_v3(
return result; return result;
} }
/******************************************************************************
******************************************************************************
**
** SELECT CRTC SOURCE
**
******************************************************************************
*****************************************************************************/
static enum bp_result select_crtc_source_v3(
struct bios_parser *bp,
struct bp_crtc_source_select *bp_params);
static void init_select_crtc_source(struct bios_parser *bp)
{
switch (BIOS_CMD_TABLE_PARA_REVISION(selectcrtc_source)) {
case 3:
bp->cmd_tbl.select_crtc_source = select_crtc_source_v3;
break;
default:
dm_output_to_console("Don't select_crtc_source enable_crtc for v%d\n",
BIOS_CMD_TABLE_PARA_REVISION(selectcrtc_source));
bp->cmd_tbl.select_crtc_source = NULL;
break;
}
}
static enum bp_result select_crtc_source_v3(
struct bios_parser *bp,
struct bp_crtc_source_select *bp_params)
{
bool result = BP_RESULT_FAILURE;
struct select_crtc_source_parameters_v2_3 params;
uint8_t atom_controller_id;
uint32_t atom_engine_id;
enum signal_type s = bp_params->signal;
memset(&params, 0, sizeof(params));
if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
&atom_controller_id))
params.crtc_id = atom_controller_id;
else
return result;
if (bp->cmd_helper->engine_bp_to_atom(bp_params->engine_id,
&atom_engine_id))
params.encoder_id = (uint8_t)atom_engine_id;
else
return result;
if (s == SIGNAL_TYPE_EDP ||
(s == SIGNAL_TYPE_DISPLAY_PORT && bp_params->sink_signal ==
SIGNAL_TYPE_LVDS))
s = SIGNAL_TYPE_LVDS;
params.encode_mode =
bp->cmd_helper->encoder_mode_bp_to_atom(
s, bp_params->enable_dp_audio);
/* Needed for VBIOS Random Spatial Dithering feature */
params.dst_bpc = (uint8_t)(bp_params->display_output_bit_depth);
if (EXEC_BIOS_CMD_TABLE(selectcrtc_source, params))
result = BP_RESULT_OK;
return result;
}
/****************************************************************************** /******************************************************************************
****************************************************************************** ******************************************************************************
** **
@ -808,7 +739,6 @@ void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
init_set_crtc_timing(bp); init_set_crtc_timing(bp);
init_select_crtc_source(bp);
init_enable_crtc(bp); init_enable_crtc(bp);
init_external_encoder_control(bp); init_external_encoder_control(bp);

3
drivers/gpu/drm/amd/display/dc/bios/command_table2.h
View File

@ -71,9 +71,6 @@ struct cmd_tbl {
enum bp_result (*set_crtc_timing)( enum bp_result (*set_crtc_timing)(
struct bios_parser *bp, struct bios_parser *bp,
struct bp_hw_crtc_timing_parameters *bp_params); struct bp_hw_crtc_timing_parameters *bp_params);
enum bp_result (*select_crtc_source)(
struct bios_parser *bp,
struct bp_crtc_source_select *bp_params);
enum bp_result (*enable_crtc)( enum bp_result (*enable_crtc)(
struct bios_parser *bp, struct bios_parser *bp,
enum controller_id controller_id, enum controller_id controller_id,

4
drivers/gpu/drm/amd/display/dc/dc_bios_types.h
View File

@ -121,10 +121,6 @@ struct dc_vbios_funcs {
enum bp_result (*program_crtc_timing)( enum bp_result (*program_crtc_timing)(
struct dc_bios *bios, struct dc_bios *bios,
struct bp_hw_crtc_timing_parameters *bp_params); struct bp_hw_crtc_timing_parameters *bp_params);
enum bp_result (*crtc_source_select)(
struct dc_bios *bios,
struct bp_crtc_source_select *bp_params);
enum bp_result (*program_display_engine_pll)( enum bp_result (*program_display_engine_pll)(
struct dc_bios *bios, struct dc_bios *bios,
struct bp_pixel_clock_parameters *bp_params); struct bp_pixel_clock_parameters *bp_params);

10
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
View File

@ -1584,6 +1584,14 @@ static void setup_stereo_sync(
REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
} }
static void dig_connect_to_otg(
struct stream_encoder *enc,
int tg_inst)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
}
static const struct stream_encoder_funcs dce110_str_enc_funcs = { static const struct stream_encoder_funcs dce110_str_enc_funcs = {
.dp_set_stream_attribute = .dp_set_stream_attribute =
@ -1618,7 +1626,7 @@ static const struct stream_encoder_funcs dce110_str_enc_funcs = {
.hdmi_audio_disable = dce110_se_hdmi_audio_disable, .hdmi_audio_disable = dce110_se_hdmi_audio_disable,
.setup_stereo_sync = setup_stereo_sync, .setup_stereo_sync = setup_stereo_sync,
.set_avmute = dce110_stream_encoder_set_avmute, .set_avmute = dce110_stream_encoder_set_avmute,
.dig_connect_to_otg = dig_connect_to_otg,
}; };
void dce110_stream_encoder_construct( void dce110_stream_encoder_construct(

8
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
View File

@ -199,7 +199,8 @@
SE_SF(DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\ SE_SF(DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
SE_SF(DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\ SE_SF(DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
SE_SF(DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\ SE_SF(DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh) SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
SE_SF(DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
#define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\ #define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\
SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
@ -284,7 +285,8 @@
SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh) SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
@ -494,6 +496,7 @@ struct dce_stream_encoder_shift {
uint8_t HDMI_DB_DISABLE; uint8_t HDMI_DB_DISABLE;
uint8_t DP_VID_N_MUL; uint8_t DP_VID_N_MUL;
uint8_t DP_VID_M_DOUBLE_VALUE_EN; uint8_t DP_VID_M_DOUBLE_VALUE_EN;
uint8_t DIG_SOURCE_SELECT;
}; };
struct dce_stream_encoder_mask { struct dce_stream_encoder_mask {
@ -624,6 +627,7 @@ struct dce_stream_encoder_mask {
uint32_t HDMI_DB_DISABLE; uint32_t HDMI_DB_DISABLE;
uint32_t DP_VID_N_MUL; uint32_t DP_VID_N_MUL;
uint32_t DP_VID_M_DOUBLE_VALUE_EN; uint32_t DP_VID_M_DOUBLE_VALUE_EN;
uint32_t DIG_SOURCE_SELECT;
}; };
struct dce110_stream_enc_registers { struct dce110_stream_enc_registers {

54
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -614,52 +614,6 @@ dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
return true; return true;
} }
static enum dc_status bios_parser_crtc_source_select(
struct pipe_ctx *pipe_ctx)
{
struct dc_bios *dcb = pipe_ctx->stream->ctx->dc_bios;
/* call VBIOS table to set CRTC source for the HW
* encoder block
* note: video bios clears all FMT setting here. */
struct bp_crtc_source_select crtc_source_select = {0};
crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id;
crtc_source_select.controller_id = pipe_ctx->stream_res.tg->inst + 1;
/*TODO: Need to un-hardcode color depth, dp_audio and account for
* the case where signal and sink signal is different (translator
* encoder)*/
crtc_source_select.signal = pipe_ctx->stream->signal;
crtc_source_select.enable_dp_audio = false;
crtc_source_select.sink_signal = pipe_ctx->stream->signal;
switch (pipe_ctx->stream->timing.display_color_depth) {
case COLOR_DEPTH_666:
crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR;
break;
case COLOR_DEPTH_888:
crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
break;
case COLOR_DEPTH_101010:
crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR;
break;
case COLOR_DEPTH_121212:
crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR;
break;
default:
BREAK_TO_DEBUGGER();
crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
break;
}
if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
dcb,
&crtc_source_select)) {
return DC_ERROR_UNEXPECTED;
}
return DC_OK;
}
void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
{ {
bool is_hdmi; bool is_hdmi;
@ -1387,12 +1341,10 @@ static enum dc_status apply_single_controller_ctx_to_hw(
/* */ /* */
dc->hwss.enable_stream_timing(pipe_ctx, context, dc); dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
/* TODO: move to stream encoder */
if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) { pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
BREAK_TO_DEBUGGER(); pipe_ctx->stream_res.stream_enc,
return DC_ERROR_UNEXPECTED; pipe_ctx->stream_res.tg->inst);
}
pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
pipe_ctx->stream_res.opp, pipe_ctx->stream_res.opp,

9
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
View File

@ -1425,6 +1425,14 @@ void enc1_setup_stereo_sync(
REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
} }
void enc1_dig_connect_to_otg(
struct stream_encoder *enc,
int tg_inst)
{
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
}
static const struct stream_encoder_funcs dcn10_str_enc_funcs = { static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
.dp_set_stream_attribute = .dp_set_stream_attribute =
@ -1457,6 +1465,7 @@ static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
.hdmi_audio_disable = enc1_se_hdmi_audio_disable, .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
.setup_stereo_sync = enc1_setup_stereo_sync, .setup_stereo_sync = enc1_setup_stereo_sync,
.set_avmute = enc1_stream_encoder_set_avmute, .set_avmute = enc1_stream_encoder_set_avmute,
.dig_connect_to_otg = enc1_dig_connect_to_otg,
}; };
void dcn10_stream_encoder_construct( void dcn10_stream_encoder_construct(

10
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
View File

@ -274,7 +274,8 @@ struct dcn10_stream_enc_registers {
SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\ SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\ SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\ SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh) SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
@ -426,7 +427,8 @@ struct dcn10_stream_enc_registers {
type DP_MSA_VHEIGHT;\ type DP_MSA_VHEIGHT;\
type HDMI_DB_DISABLE;\ type HDMI_DB_DISABLE;\
type DP_VID_N_MUL;\ type DP_VID_N_MUL;\
type DP_VID_M_DOUBLE_VALUE_EN type DP_VID_M_DOUBLE_VALUE_EN;\
type DIG_SOURCE_SELECT
struct dcn10_stream_encoder_shift { struct dcn10_stream_encoder_shift {
SE_REG_FIELD_LIST_DCN1_0(uint8_t); SE_REG_FIELD_LIST_DCN1_0(uint8_t);
@ -523,4 +525,8 @@ void enc1_se_hdmi_audio_setup(
void enc1_se_hdmi_audio_disable( void enc1_se_hdmi_audio_disable(
struct stream_encoder *enc); struct stream_encoder *enc);
void enc1_dig_connect_to_otg(
struct stream_encoder *enc,
int tg_inst);
#endif /* __DC_STREAM_ENCODER_DCN10_H__ */ #endif /* __DC_STREAM_ENCODER_DCN10_H__ */

4
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
View File

@ -161,6 +161,10 @@ struct stream_encoder_funcs {
void (*set_avmute)( void (*set_avmute)(
struct stream_encoder *enc, bool enable); struct stream_encoder *enc, bool enable);
void (*dig_connect_to_otg)(
struct stream_encoder *enc,
int tg_inst);
}; };
#endif /* STREAM_ENCODER_H_ */ #endif /* STREAM_ENCODER_H_ */