From d3c9a44103e98f2722c8b8c48b604995f5063034 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 27 Mar 2024 09:10:37 +0200 Subject: [PATCH] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GPU With the clkcsel binding we can drop the custom ti,bit-shift devicetree property in favor of the standard reg property and reduce the number of clocks to update for the make W-1 dtbs warnings. Let's also add a comment for the clocksel clock that matches the documentation. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi index 88c14c172b0f..a7667d954ec5 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -476,13 +476,21 @@ clock-div = <1>; }; - dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_gpu_byp_mux"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x02e4>; + /* CM_CLKSEL_DPLL_GPU */ + clock@2e4 { + compatible = "ti,clksel"; + reg = <0x2e4>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + dpll_gpu_byp_mux: clock@23 { + reg = <23>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_gpu_byp_mux"; + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; + #clock-cells = <0>; + }; }; dpll_gpu_ck: clock@2d8 {