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drm/i915/guc/slpc: Add methods to set min/max frequency

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Add param set h2g helpers to set the min and max frequencies
for use by SLPC.

v2: Address review comments (Michal W)
v3: Check for positive error code (Michal W)
v4: Print generic error in set_param (Michal W)

Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Sundaresan Sujaritha <sujaritha.sundaresan@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210730202119.23810-8-vinay.belgaumkar@intel.com
This commit is contained in:
Vinay Belgaumkar 2021-07-30 13:21:12 -07:00 committed by John Harrison
parent db301cffd8
commit d41f6f82d3
2 changed files with 91 additions and 0 deletions
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89
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
View File

@ -111,6 +111,21 @@ static u32 slpc_get_state(struct intel_guc_slpc *slpc)
return data->header.global_state;
}
static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
{
u32 request[] = {
GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),
id,
value,
};
int ret;
ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
return ret > 0 ? -EPROTO : ret;
}
static bool slpc_is_running(struct intel_guc_slpc *slpc)
{
return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
@ -148,6 +163,22 @@ static int slpc_query_task_state(struct intel_guc_slpc *slpc)
return ret;
}
static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
{
struct intel_guc *guc = slpc_to_guc(slpc);
struct drm_i915_private *i915 = slpc_to_i915(slpc);
int ret;
GEM_BUG_ON(id >= SLPC_MAX_PARAM);
ret = guc_action_slpc_set_param(guc, id, value);
if (ret)
drm_err(&i915->drm, "Failed to set param %d to %u (%pe)\n",
id, value, ERR_PTR(ret));
return ret;
}
static const char *slpc_global_state_to_string(enum slpc_global_state state)
{
switch (state) {
@ -231,6 +262,64 @@ static void slpc_shared_data_reset(struct slpc_shared_data *data)
SLPC_PARAM_TASK_DISABLE_DCC);
}
/**
* intel_guc_slpc_set_max_freq() - Set max frequency limit for SLPC.
* @slpc: pointer to intel_guc_slpc.
* @val: frequency (MHz)
*
* This function will invoke GuC SLPC action to update the max frequency
* limit for unslice.
*
* Return: 0 on success, non-zero error code on failure.
*/
int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
{
struct drm_i915_private *i915 = slpc_to_i915(slpc);
intel_wakeref_t wakeref;
int ret;
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
ret = slpc_set_param(slpc,
SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
val);
/* Return standardized err code for sysfs calls */
if (ret)
ret = -EIO;
}
return ret;
}
/**
* intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
* @slpc: pointer to intel_guc_slpc.
* @val: frequency (MHz)
*
* This function will invoke GuC SLPC action to update the min unslice
* frequency.
*
* Return: 0 on success, non-zero error code on failure.
*/
int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
{
struct drm_i915_private *i915 = slpc_to_i915(slpc);
intel_wakeref_t wakeref;
int ret;
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
ret = slpc_set_param(slpc,
SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
val);
/* Return standardized err code for sysfs calls */
if (ret)
ret = -EIO;
}
return ret;
}
/*
* intel_guc_slpc_enable() - Start SLPC
* @slpc: pointer to intel_guc_slpc.

2
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
View File

@ -29,5 +29,7 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc);
int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val);
int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val);
#endif