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Devicetree updates for v6.4, part 1:

Browse Source 
Bindings:
 - Convert Qcom IOMMU, Amlogic timer, Freescale sec-v4.0, Toshiba
   TC358764 display bridge, Parade PS8622 display bridge, and  Xilinx
   FPGA bindings to DT schema format
 
 - Add qdu1000 and sa8775p SoC support to Qcom PDC interrupt controller
 
 - Add MediaTek MT8365 UART and SYSIRQ bindings
 
 - Add Arm Cortex-A78C and X1C core compatibles
 
 - Add vendor prefix for Novatek
 
 - Remove bindings for stih415, sti416, stid127 platforms
 
 - Drop uneeded quotes in schema files. This is preparation for yamllint
   checking quoting for us.
 
 - Add missing (unevaluated|additional)Properties constraints on child
   node schemas
 
 - Clean-up schema comments formatting
 
 - Fix I2C and SPI node bus names in schema examples
 
 - Clean-up some display compatibles schema syntax
 
 - Fix incorrect references to lvds.yaml
 
 - Gather all cache controller bindings in a common directory
 
 DT core:
 - Convert unittest to new void .remove platform device hook
 
 - kerneldoc fixes for DT address of_pci_range_to_resource/
   of_address_to_resource functions
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Merge tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:
 "Bindings:

   - Convert Qcom IOMMU, Amlogic timer, Freescale sec-v4.0, Toshiba
     TC358764 display bridge, Parade PS8622 display bridge, and Xilinx
     FPGA bindings to DT schema format

   - Add qdu1000 and sa8775p SoC support to Qcom PDC interrupt
     controller

   - Add MediaTek MT8365 UART and SYSIRQ bindings

   - Add Arm Cortex-A78C and X1C core compatibles

   - Add vendor prefix for Novatek

   - Remove bindings for stih415, sti416, stid127 platforms

   - Drop uneeded quotes in schema files. This is preparation for
     yamllint checking quoting for us.

   - Add missing (unevaluated|additional)Properties constraints on child
     node schemas

   - Clean-up schema comments formatting

   - Fix I2C and SPI node bus names in schema examples

   - Clean-up some display compatibles schema syntax

   - Fix incorrect references to lvds.yaml

   - Gather all cache controller bindings in a common directory

  DT core:

   - Convert unittest to new void .remove platform device hook

   - kerneldoc fixes for DT address of_pci_range_to_resource/
     of_address_to_resource functions"

* tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (46 commits)
  dt-bindings: rng: Drop unneeded quotes
  dt-bindings: arm/soc: mediatek: Drop unneeded quotes
  dt-bindings: soc: qcom: Drop unneeded quotes
  dt-bindings: i2c: samsung: Fix 'deprecated' value
  dt-bindings: display: Fix lvds.yaml references
  dt-bindings: display: simplify compatibles syntax
  dt-bindings: display: mediatek: simplify compatibles syntax
  dt-bindings: drm/bridge: ti-sn65dsi86: Fix the video-interfaces.yaml references
  dt-bindings: timer: Drop unneeded quotes
  dt-bindings: interrupt-controller: qcom,pdc: document qcom,qdu1000-pdc
  dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p
  dt-bindings: reset: remove stih415/stih416 reset
  dt-bindings: net: dwmac: sti: remove stih415/sti416/stid127
  dt-bindings: irqchip: sti: remove stih415/stih416 and stid127
  dt-bindings: iommu: Convert QCOM IOMMU to YAML
  dt-bindings: irqchip: ti,sci-inta: Add optional power-domains property
  dt-bindings: Add missing (unevaluated|additional)Properties on child node schemas
  of: address: Reshuffle to remove forward declarations
  of: address: Fix documented return value of of_pci_range_to_resource()
  of: address: Document return value of of_address_to_resource()
  ...
This commit is contained in:
Linus Torvalds 2023-04-27 09:23:57 -07:00
commit d42b1c4757
322 changed files with 1611 additions and 1589 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/.yamllint
View File

@ -19,7 +19,7 @@ rules:
colons: {max-spaces-before: 0, max-spaces-after: 1}
commas: {min-spaces-after: 1, max-spaces-after: 1}
comments:
require-starting-space: false
require-starting-space: true
min-spaces-from-content: 1
comments-indentation: disable
document-start:

1
Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
View File

@ -144,6 +144,7 @@ patternProperties:
it is stricter and always has two compatibles.
type: object
$ref: '/schemas/simple-bus.yaml'
unevaluatedProperties: false
properties:
compatible:

5
Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
View File

@ -30,6 +30,7 @@ properties:
clocks:
type: object
additionalProperties: false
properties:
compatible:
@ -47,6 +48,7 @@ properties:
reset:
type: object
additionalProperties: false
properties:
compatible:
@ -63,6 +65,7 @@ properties:
pwm:
type: object
additionalProperties: false
properties:
compatible:
@ -76,8 +79,6 @@ properties:
- compatible
- "#pwm-cells"
additionalProperties: false
required:
- compatible
- mboxes

2
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@ -141,6 +141,7 @@ properties:
- arm,cortex-a77
- arm,cortex-a78
- arm,cortex-a78ae
- arm,cortex-a78c
- arm,cortex-a510
- arm,cortex-a710
- arm,cortex-a715
@ -153,6 +154,7 @@ properties:
- arm,cortex-r5
- arm,cortex-r7
- arm,cortex-x1
- arm,cortex-x1c
- arm,cortex-x2
- arm,cortex-x3
- arm,neoverse-e1

4
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Infrastructure System Configuration Controller

4
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek mmsys controller

4
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml
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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek PCIE Mirror Controller for MT7622

4
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml
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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Wireless Ethernet Dispatch Controller for MT7622

4
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml
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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek PCIE WED Controller for MT7986

4
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8186

4
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT8186

4
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8192

4
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT8192

4
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8195

4
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT8195

4
Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Peripheral Configuration Controller

4
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
View File

@ -234,6 +234,7 @@ properties:
patternProperties:
"^[a-z0-9]+$":
type: object
additionalProperties: false
properties:
clocks:
@ -252,6 +253,9 @@ properties:
for controlling a power-gate.
See ../reset/reset.txt for more details.
power-domains:
maxItems: 1
'#power-domain-cells':
const: 0
description: Must be 0.

6
Documentation/devicetree/bindings/ata/ahci-common.yaml
View File

@ -59,7 +59,7 @@ properties:
const: sata-phy
hba-cap:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description:
Bitfield of the HBA generic platform capabilities like Staggered
Spin-up or Mechanical Presence Switch support. It can be used to
@ -67,7 +67,7 @@ properties:
in case if the system firmware hasn't done it.
ports-implemented:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description:
Mask that indicates which ports the HBA supports. Useful if PI is not
programmed by the BIOS, which is true for some embedded SoC's.
@ -110,7 +110,7 @@ $defs:
description: Power regulator for SATA port target device
hba-port-cap:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description:
Bitfield of the HBA port-specific platform capabilities like Hot
plugging, eSATA, FIS-based Switching, etc (see AHCI specification

4
Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml
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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car Serial-ATA Interface

2
Documentation/devicetree/bindings/auxdisplay/holtek,ht16k33.yaml
View File

@ -72,7 +72,7 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;

1
Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml
View File

@ -46,6 +46,7 @@ patternProperties:
# All other properties should be child nodes with unit-address and 'reg'
"^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+$":
type: object
additionalProperties: true
properties:
reg:
maxItems: 1

1
Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml
View File

@ -45,6 +45,7 @@ properties:
patternProperties:
"^.*@[0-9a-fA-F]+$":
type: object
additionalProperties: true
properties:
reg:
maxItems: 1

1
Documentation/devicetree/bindings/bus/palmbus.yaml
View File

@ -36,6 +36,7 @@ patternProperties:
# All other properties should be child nodes with unit-address and 'reg'
"@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
reg:
maxItems: 1

2
Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml → Documentation/devicetree/bindings/cache/baikal,bt1-l2-ctl.yaml vendored
View File

@ -2,7 +2,7 @@
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#
$id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Baikal-T1 L2-cache Control Block

0
Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt → Documentation/devicetree/bindings/cache/freescale-l2cache.txt vendored
View File

2
Documentation/devicetree/bindings/arm/l2c2x0.yaml → Documentation/devicetree/bindings/cache/l2c2x0.yaml vendored
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/l2c2x0.yaml#
$id: http://devicetree.org/schemas/cache/l2c2x0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM L2 Cache Controller

0
Documentation/devicetree/bindings/arm/mrvl/feroceon.txt → Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt vendored
View File

0
Documentation/devicetree/bindings/arm/mrvl/tauros2.txt → Documentation/devicetree/bindings/cache/marvell,tauros2-cache.txt vendored
View File

2
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml → Documentation/devicetree/bindings/cache/qcom,llcc.yaml vendored
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
$id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Last Level Cache Controller

2
Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml → Documentation/devicetree/bindings/cache/sifive,ccache0.yaml vendored
View File

@ -2,7 +2,7 @@
# Copyright (C) 2020 SiFive, Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml#
$id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive Composable Cache Controller

2
Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml → Documentation/devicetree/bindings/cache/socionext,uniphier-system-cache.yaml vendored
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
$id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier outer cache controller

2
Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
View File

@ -41,7 +41,7 @@ additionalProperties: false
examples:
- |+
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;

2
Documentation/devicetree/bindings/chrome/google,cros-kbd-led-backlight.yaml
View File

@ -20,7 +20,7 @@ additionalProperties: false
examples:
- |
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;

4
Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml
View File

@ -81,11 +81,11 @@ properties:
maxItems: 1
lock-offset:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description: Offset to the unlocking register for the oscillator
vco-offset:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description: Offset to the VCO register for the oscillator
deprecated: true

4
Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
View File

@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek AP Mixedsys Controller

4
Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
View File

@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Top Clock Generator Controller

4
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
View File

@ -45,14 +45,14 @@ required:
additionalProperties: false
examples:
#Example 1 - A53 PLL found on MSM8916 devices
# Example 1 - A53 PLL found on MSM8916 devices
- |
a53pll: clock@b016000 {
compatible = "qcom,msm8916-a53pll";
reg = <0xb016000 0x40>;
#clock-cells = <0>;
};
#Example 2 - A53 PLL found on IPQ6018 devices
# Example 2 - A53 PLL found on IPQ6018 devices
- |
a53pll_ipq: clock-controller@b116000 {
compatible = "qcom,ipq6018-a53pll";

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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas Clock Pulse Generator / Module Standby and Software Reset

4
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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car USB 2.0 clock selector

4
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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode

2
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@ -202,7 +202,7 @@ allOf:
- description: External RTC clock (32768 Hz)
- description: CMU_HSI bus clock (from CMU_TOP)
- description: SD card clock (from CMU_TOP)
- description: "USB 2.0 DRD clock (from CMU_TOP)"
- description: USB 2.0 DRD clock (from CMU_TOP)
clock-names:
items:

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@ -2,8 +2,8 @@
# Copyright 2019 Unisoc Inc.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SC9863A Clock Control Unit

4
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@ -2,8 +2,8 @@
# Copyright 2022 Unisoc Inc.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UMS512 Soc clock controller

2
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@ -160,7 +160,7 @@ examples:
};
};
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;

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@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx clocking wizard

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# SPDX-License-Identifier: GPL-2.0
# Copyright (C) 2008-2011 Freescale Semiconductor Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0-mon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Secure Non-Volatile Storage (SNVS)
maintainers:
- '"Horia Geantă" <horia.geanta@nxp.com>'
- Pankaj Gupta <pankaj.gupta@nxp.com>
- Gaurav Jain <gaurav.jain@nxp.com>
description:
Node defines address range and the associated interrupt for the SNVS function.
This function monitors security state information & reports security
violations. This also included rtc, system power off and ON/OFF key.
properties:
compatible:
oneOf:
- items:
- const: fsl,sec-v4.0-mon
- const: syscon
- const: simple-mfd
- items:
- const: fsl,sec-v5.0-mon
- const: fsl,sec-v4.0-mon
- items:
- enum:
- fsl,sec-v5.3-mon
- fsl,sec-v5.4-mon
- const: fsl,sec-v5.0-mon
- const: fsl,sec-v4.0-mon
reg:
maxItems: 1
interrupts:
maxItems: 2
snvs-rtc-lp:
type: object
additionalProperties: false
description:
Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
properties:
compatible:
const: fsl,sec-v4.0-mon-rtc-lp
clocks:
maxItems: 1
clock-names:
const: snvs-rtc
interrupts:
# VFxxx has only one. What is the 2nd one?
minItems: 1
maxItems: 2
regmap:
description: Parent node containing registers
$ref: /schemas/types.yaml#/definitions/phandle
offset:
description: LP register offset
$ref: /schemas/types.yaml#/definitions/uint32
default: 0x34
required:
- compatible
- interrupts
- regmap
snvs-powerkey:
type: object
additionalProperties: false
description:
The snvs-pwrkey is designed to enable POWER key function which controlled
by SNVS ONOFF, the driver can report the status of POWER key and wakeup
system if pressed after system suspend.
properties:
compatible:
const: fsl,sec-v4.0-pwrkey
clocks:
maxItems: 1
clock-names:
const: snvs-pwrkey
interrupts:
maxItems: 1
regmap:
description: Parent node containing registers
$ref: /schemas/types.yaml#/definitions/phandle
wakeup-source: true
linux,keycode:
default: 116
required:
- compatible
- interrupts
- regmap
snvs-lpgpr:
$ref: /schemas/nvmem/snvs-lpgpr.yaml#
snvs-poweroff:
description:
The SNVS could drive signal to PMIC to turn off system power by setting
SNVS_LP LPCR register.
$ref: /schemas/power/reset/syscon-poweroff.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imx7d-clock.h>
sec_mon: sec-mon@314000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x314000 0x1000>;
snvs-rtc-lp {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap = <&sec_mon>;
offset = <0x34>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-rtc";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
};
snvs-powerkey {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&sec_mon>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-pwrkey";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <116>; /* KEY_POWER */
wakeup-source;
};
};

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# SPDX-License-Identifier: GPL-2.0
# Copyright (C) 2008-2011 Freescale Semiconductor Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale SEC 4
maintainers:
- '"Horia Geantă" <horia.geanta@nxp.com>'
- Pankaj Gupta <pankaj.gupta@nxp.com>
- Gaurav Jain <gaurav.jain@nxp.com>
description: |
NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
Accelerator and Assurance Module (CAAM).
SEC 4 h/w can process requests from 2 types of sources.
1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
2. Job Rings (HW interface between cores & SEC 4 registers).
High Speed Data Path Configuration:
HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
such as the P4080. The number of simultaneous dequeues the QI can make is
equal to the number of Descriptor Controller (DECO) engines in a particular
SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
dequeue from 5 subportals simultaneously.
Job Ring Data Path Configuration:
Each JR is located on a separate 4k page, they may (or may not) be made visible
in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
properties:
compatible:
oneOf:
- items:
- const: fsl,sec-v5.4
- const: fsl,sec-v5.0
- const: fsl,sec-v4.0
- items:
- enum:
- fsl,imx6ul-caam
- fsl,sec-v5.0
- const: fsl,sec-v4.0
- const: fsl,sec-v4.0
reg:
maxItems: 1
ranges:
maxItems: 1
'#address-cells':
enum: [1, 2]
'#size-cells':
enum: [1, 2]
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
maxItems: 4
items:
enum: [mem, aclk, ipg, emi_slow]
dma-coherent: true
interrupts:
maxItems: 1
fsl,sec-era:
description: Defines the 'ERA' of the SEC device.
$ref: /schemas/types.yaml#/definitions/uint32
patternProperties:
'^jr@[0-9a-f]+$':
type: object
additionalProperties: false
description:
Job Ring (JR) Node. Defines data processing interface to SEC 4 across the
peripheral bus for purposes of processing cryptographic descriptors. The
specified address range can be made visible to one (or more) cores. The
interrupt defined for this node is controlled within the address range of
this node.
properties:
compatible:
oneOf:
- items:
- const: fsl,sec-v5.4-job-ring
- const: fsl,sec-v5.0-job-ring
- const: fsl,sec-v4.0-job-ring
- items:
- const: fsl,sec-v5.0-job-ring
- const: fsl,sec-v4.0-job-ring
- const: fsl,sec-v4.0-job-ring
reg:
maxItems: 1
interrupts:
maxItems: 1
fsl,liodn:
description:
Specifies the LIODN to be used in conjunction with the ppid-to-liodn
table that specifies the PPID to LIODN mapping. Needed if the PAMU is
used. Value is a 12 bit value where value is a LIODN ID for this JR.
This property is normally set by boot firmware.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 0xfff
'^rtic@[0-9a-f]+$':
type: object
additionalProperties: false
description:
Run Time Integrity Check (RTIC) Node. Defines a register space that
contains up to 5 sets of addresses and their lengths (sizes) that will be
checked at run time. After an initial hash result is calculated, these
addresses are checked by HW to monitor any change. If any memory is
modified, a Security Violation is triggered (see SNVS definition).
properties:
compatible:
oneOf:
- items:
- const: fsl,sec-v5.4-rtic
- const: fsl,sec-v5.0-rtic
- const: fsl,sec-v4.0-rtic
- const: fsl,sec-v4.0-rtic
reg:
maxItems: 1
ranges:
maxItems: 1
interrupts:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 1
patternProperties:
'^rtic-[a-z]@[0-9a-f]+$':
type: object
additionalProperties: false
description:
Run Time Integrity Check (RTIC) Memory Node defines individual RTIC
memory regions that are used to perform run-time integrity check of
memory areas that should not modified. The node defines a register
that contains the memory address & length (combined) and a second
register that contains the hash result in big endian format.
properties:
compatible:
oneOf:
- items:
- const: fsl,sec-v5.4-rtic-memory
- const: fsl,sec-v5.0-rtic-memory
- const: fsl,sec-v4.0-rtic-memory
- const: fsl,sec-v4.0-rtic-memory
reg:
items:
- description: RTIC memory address
- description: RTIC hash result
fsl,liodn:
description:
Specifies the LIODN to be used in conjunction with the
ppid-to-liodn table that specifies the PPID to LIODN mapping.
Needed if the PAMU is used. Value is a 12 bit value where value
is a LIODN ID for this JR. This property is normally set by boot
firmware.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 0xfff
fsl,rtic-region:
description:
Specifies the HW address (36 bit address) for this region
followed by the length of the HW partition to be checked;
the address is represented as a 64 bit quantity followed
by a 32 bit length.
$ref: /schemas/types.yaml#/definitions/uint32-array
required:
- compatible
- reg
- ranges
additionalProperties: false
examples:
- |
crypto@300000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
ranges = <0 0x300000 0x10000>;
interrupts = <92 2>;
jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <88 2>;
};
jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <89 2>;
};
jr@3000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <90 2>;
};
jr@4000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x4000 0x1000>;
interrupts = <91 2>;
};
rtic@6000 {
compatible = "fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
ranges = <0x0 0x6100 0xe00>;
rtic-a@0 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20>, <0x100 0x80>;
};
rtic-b@20 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x20 0x20>, <0x200 0x80>;
};
rtic-c@40 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x40 0x20>, <0x300 0x80>;
};
rtic-d@60 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x60 0x20>, <0x500 0x80>;
};
};
};
...

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=====================================================================
SEC 4 Device Tree Binding
Copyright (C) 2008-2011 Freescale Semiconductor Inc.
CONTENTS
-Overview
-SEC 4 Node
-Job Ring Node
-Run Time Integrity Check (RTIC) Node
-Run Time Integrity Check (RTIC) Memory Node
-Secure Non-Volatile Storage (SNVS) Node
-Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
-Full Example
NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
Accelerator and Assurance Module (CAAM).
=====================================================================
Overview
DESCRIPTION
SEC 4 h/w can process requests from 2 types of sources.
1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
2. Job Rings (HW interface between cores & SEC 4 registers).
High Speed Data Path Configuration:
HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
such as the P4080. The number of simultaneous dequeues the QI can make is
equal to the number of Descriptor Controller (DECO) engines in a particular
SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
dequeue from 5 subportals simultaneously.
Job Ring Data Path Configuration:
Each JR is located on a separate 4k page, they may (or may not) be made visible
in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
=====================================================================
SEC 4 Node
Description
Node defines the base address of the SEC 4 block.
This block specifies the address range of all global
configuration registers for the SEC 4 block. It
also receives interrupts from the Run Time Integrity Check
(RTIC) function within the SEC 4 block.
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,sec-v4.0"
- fsl,sec-era
Usage: optional
Value type: <u32>
Definition: A standard property. Define the 'ERA' of the SEC
device.
- #address-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
for representing physical addresses in child nodes.
- #size-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
for representing the size of physical addresses in
child nodes.
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical
address and length of the SEC4 configuration registers.
registers
- ranges
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
range of the SEC 4.0 register space (-SNVS not included). A
triplet that includes the child address, parent address, &
length.
- interrupts
Usage: required
Value type: <prop_encoded-array>
Definition: Specifies the interrupts generated by this
device. The value of the interrupts property
consists of one interrupt specifier. The format
of the specifier is defined by the binding document
describing the node's interrupt parent.
- clocks
Usage: required if SEC 4.0 requires explicit enablement of clocks
Value type: <prop_encoded-array>
Definition: A list of phandle and clock specifier pairs describing
the clocks required for enabling and disabling SEC 4.0.
- clock-names
Usage: required if SEC 4.0 requires explicit enablement of clocks
Value type: <string>
Definition: A list of clock name strings in the same order as the
clocks property.
Note: All other standard properties (see the Devicetree Specification)
are allowed but are optional.
EXAMPLE
iMX6QDL/SX requires four clocks
crypto@300000 {
compatible = "fsl,sec-v4.0";
fsl,sec-era = <2>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
ranges = <0 0x300000 0x10000>;
interrupt-parent = <&mpic>;
interrupts = <92 2>;
clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
<&clks IMX6QDL_CLK_CAAM_ACLK>,
<&clks IMX6QDL_CLK_CAAM_IPG>,
<&clks IMX6QDL_CLK_EIM_SLOW>;
clock-names = "mem", "aclk", "ipg", "emi_slow";
};
iMX6UL does only require three clocks
crypto: crypto@2140000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2140000 0x3c000>;
ranges = <0 0x2140000 0x3c000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_CAAM_MEM>,
<&clks IMX6UL_CLK_CAAM_ACLK>,
<&clks IMX6UL_CLK_CAAM_IPG>;
clock-names = "mem", "aclk", "ipg";
};
=====================================================================
Job Ring (JR) Node
Child of the crypto node defines data processing interface to SEC 4
across the peripheral bus for purposes of processing
cryptographic descriptors. The specified address
range can be made visible to one (or more) cores.
The interrupt defined for this node is controlled within
the address range of this node.
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,sec-v4.0-job-ring"
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: Specifies a two JR parameters: an offset from
the parent physical address and the length the JR registers.
- fsl,liodn
Usage: optional-but-recommended
Value type: <prop-encoded-array>
Definition:
Specifies the LIODN to be used in conjunction with
the ppid-to-liodn table that specifies the PPID to LIODN mapping.
Needed if the PAMU is used. Value is a 12 bit value
where value is a LIODN ID for this JR. This property is
normally set by boot firmware.
- interrupts
Usage: required
Value type: <prop_encoded-array>
Definition: Specifies the interrupts generated by this
device. The value of the interrupts property
consists of one interrupt specifier. The format
of the specifier is defined by the binding document
describing the node's interrupt parent.
EXAMPLE
jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
fsl,liodn = <0x081>;
interrupt-parent = <&mpic>;
interrupts = <88 2>;
};
=====================================================================
Run Time Integrity Check (RTIC) Node
Child node of the crypto node. Defines a register space that
contains up to 5 sets of addresses and their lengths (sizes) that
will be checked at run time. After an initial hash result is
calculated, these addresses are checked by HW to monitor any
change. If any memory is modified, a Security Violation is
triggered (see SNVS definition).
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,sec-v4.0-rtic".
- #address-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
for representing physical addresses in child nodes. Must
have a value of 1.
- #size-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
for representing the size of physical addresses in
child nodes. Must have a value of 1.
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies a two parameters:
an offset from the parent physical address and the length
the SEC4 registers.
- ranges
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
range of the SEC 4 register space (-SNVS not included). A
triplet that includes the child address, parent address, &
length.
EXAMPLE
rtic@6000 {
compatible = "fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
ranges = <0x0 0x6100 0xe00>;
};
=====================================================================
Run Time Integrity Check (RTIC) Memory Node
A child node that defines individual RTIC memory regions that are used to
perform run-time integrity check of memory areas that should not modified.
The node defines a register that contains the memory address &
length (combined) and a second register that contains the hash result
in big endian format.
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,sec-v4.0-rtic-memory".
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies two parameters:
an offset from the parent physical address and the length:
1. The location of the RTIC memory address & length registers.
2. The location RTIC hash result.
- fsl,rtic-region
Usage: optional-but-recommended
Value type: <prop-encoded-array>
Definition:
Specifies the HW address (36 bit address) for this region
followed by the length of the HW partition to be checked;
the address is represented as a 64 bit quantity followed
by a 32 bit length.
- fsl,liodn
Usage: optional-but-recommended
Value type: <prop-encoded-array>
Definition:
Specifies the LIODN to be used in conjunction with
the ppid-to-liodn table that specifies the PPID to LIODN
mapping. Needed if the PAMU is used. Value is a 12 bit value
where value is a LIODN ID for this RTIC memory region. This
property is normally set by boot firmware.
EXAMPLE
rtic-a@0 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20 0x100 0x80>;
fsl,liodn = <0x03c>;
fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
};
=====================================================================
Secure Non-Volatile Storage (SNVS) Node
Node defines address range and the associated
interrupt for the SNVS function. This function
monitors security state information & reports
security violations. This also included rtc,
system power off and ON/OFF key.
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,sec-v4.0-mon" and "syscon".
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical
address and length of the SEC4 configuration
registers.
- #address-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
for representing physical addresses in child nodes. Must
have a value of 1.
- #size-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
for representing the size of physical addresses in
child nodes. Must have a value of 1.
- ranges
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
range of the SNVS register space. A triplet that includes
the child address, parent address, & length.
- interrupts
Usage: optional
Value type: <prop_encoded-array>
Definition: Specifies the interrupts generated by this
device. The value of the interrupts property
consists of one interrupt specifier. The format
of the specifier is defined by the binding document
describing the node's interrupt parent.
EXAMPLE
sec_mon@314000 {
compatible = "fsl,sec-v4.0-mon", "syscon";
reg = <0x314000 0x1000>;
ranges = <0 0x314000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <93 2>;
};
=====================================================================
Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
A SNVS child node that defines SNVS LP RTC.
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
- interrupts
Usage: required
Value type: <prop_encoded-array>
Definition: Specifies the interrupts generated by this
device. The value of the interrupts property
consists of one interrupt specifier. The format
of the specifier is defined by the binding document
describing the node's interrupt parent.
- regmap
Usage: required
Value type: <phandle>
Definition: this is phandle to the register map node.
- offset
Usage: option
value type: <u32>
Definition: LP register offset. default it is 0x34.
- clocks
Usage: optional, required if SNVS LP RTC requires explicit
enablement of clocks
Value type: <prop_encoded-array>
Definition: a clock specifier describing the clock required for
enabling and disabling SNVS LP RTC.
- clock-names
Usage: optional, required if SNVS LP RTC requires explicit
enablement of clocks
Value type: <string>
Definition: clock name string should be "snvs-rtc".
EXAMPLE
sec_mon_rtc_lp@1 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
interrupts = <93 2>;
regmap = <&snvs>;
offset = <0x34>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-rtc";
};
=====================================================================
System ON/OFF key driver
The snvs-pwrkey is designed to enable POWER key function which controlled
by SNVS ONOFF, the driver can report the status of POWER key and wakeup
system if pressed after system suspend.
- compatible:
Usage: required
Value type: <string>
Definition: Mush include "fsl,sec-v4.0-pwrkey".
- interrupts:
Usage: required
Value type: <prop_encoded-array>
Definition: The SNVS ON/OFF interrupt number to the CPU(s).
- linux,keycode:
Usage: option
Value type: <int>
Definition: Keycode to emit, KEY_POWER by default.
- wakeup-source:
Usage: option
Value type: <boo>
Definition: Button can wake-up the system.
- regmap:
Usage: required:
Value type: <phandle>
Definition: this is phandle to the register map node.
EXAMPLE:
snvs-pwrkey@020cc000 {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&snvs>;
interrupts = <0 4 0x4>
linux,keycode = <116>; /* KEY_POWER */
wakeup-source;
};
=====================================================================
FULL EXAMPLE
crypto: crypto@300000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
ranges = <0 0x300000 0x10000>;
interrupt-parent = <&mpic>;
interrupts = <92 2>;
sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <88 2>;
};
sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <89 2>;
};
sec_jr2: jr@3000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <90 2>;
};
sec_jr3: jr@4000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x4000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <91 2>;
};
rtic@6000 {
compatible = "fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
ranges = <0x0 0x6100 0xe00>;
rtic_a: rtic-a@0 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20 0x100 0x80>;
};
rtic_b: rtic-b@20 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x20 0x20 0x200 0x80>;
};
rtic_c: rtic-c@40 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x40 0x20 0x300 0x80>;
};
rtic_d: rtic-d@60 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x60 0x20 0x500 0x80>;
};
};
};
sec_mon: sec_mon@314000 {
compatible = "fsl,sec-v4.0-mon";
reg = <0x314000 0x1000>;
ranges = <0 0x314000 0x1000>;
sec_mon_rtc_lp@34 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap = <&sec_mon>;
offset = <0x34>;
interrupts = <93 2>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-rtc";
};
snvs-pwrkey@020cc000 {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&sec_mon>;
interrupts = <0 4 0x4>;
linux,keycode = <116>; /* KEY_POWER */
wakeup-source;
};
};
=====================================================================

4
Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml
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@ -26,8 +26,8 @@ properties:
dmas:
items:
- description: TX DMA Channel
- description: RX DMA Channel #1
- description: RX DMA Channel #2
- description: 'RX DMA Channel #1'
- description: 'RX DMA Channel #2'
dma-names:
items:

5
Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
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@ -16,8 +16,7 @@ description: |
properties:
compatible:
items:
- const: analogix,anx7625
const: analogix,anx7625
reg:
maxItems: 1
@ -134,7 +133,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;

2
Documentation/devicetree/bindings/display/bridge/anx6345.yaml
View File

@ -61,7 +61,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;

2
Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml
View File

@ -67,7 +67,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c4 {
i2c {
#address-cells = <1>;
#size-cells = <0>;

2
Documentation/devicetree/bindings/display/bridge/nxp,ptn3460.yaml
View File

@ -71,7 +71,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;

115
Documentation/devicetree/bindings/display/bridge/parade,ps8622.yaml Normal file
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@ -0,0 +1,115 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/parade,ps8622.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Parade PS8622/PS8625 DisplayPort to LVDS Converter
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
properties:
compatible:
enum:
- parade,ps8622
- parade,ps8625
reg:
maxItems: 1
lane-count:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2]
description: Number of DP lanes to use.
use-external-pwm:
type: boolean
description: Backlight will be controlled by an external PWM.
reset-gpios:
maxItems: 1
description: GPIO connected to RST_ pin.
sleep-gpios:
maxItems: 1
description: GPIO connected to PD_ pin.
vdd12-supply: true
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Video port for LVDS output.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Video port for DisplayPort input.
required:
- port@0
- port@1
required:
- compatible
- reg
- reset-gpios
- sleep-gpios
- ports
allOf:
- if:
properties:
compatible:
const: parade,ps8622
then:
properties:
lane-count:
const: 1
else:
properties:
lane-count:
const: 2
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
lvds-bridge@48 {
compatible = "parade,ps8625";
reg = <0x48>;
sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>;
lane-count = <2>;
use-external-pwm;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
port@1 {
reg = <1>;
bridge_in: endpoint {
remote-endpoint = <&dp_out>;
};
};
};
};
};

31
Documentation/devicetree/bindings/display/bridge/ps8622.txt
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@ -1,31 +0,0 @@
ps8622-bridge bindings
Required properties:
- compatible: "parade,ps8622" or "parade,ps8625"
- reg: first i2c address of the bridge
- sleep-gpios: OF device-tree gpio specification for PD_ pin.
- reset-gpios: OF device-tree gpio specification for RST_ pin.
Optional properties:
- lane-count: number of DP lanes to use
- use-external-pwm: backlight will be controlled by an external PWM
- video interfaces: Device node can contain video interface port
nodes for panel according to [1].
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
lvds-bridge@48 {
compatible = "parade,ps8622";
reg = <0x48>;
sleep-gpios = <&gpc3 6 1 0 0>;
reset-gpios = <&gpc3 1 1 0 0>;
lane-count = <1>;
ports {
port@0 {
bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};

2
Documentation/devicetree/bindings/display/bridge/ps8640.yaml
View File

@ -73,7 +73,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;

2
Documentation/devicetree/bindings/display/bridge/sil,sii9234.yaml
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@ -71,7 +71,7 @@ examples:
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;

2
Documentation/devicetree/bindings/display/bridge/ti,dlpc3433.yaml
View File

@ -83,7 +83,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;

6
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml
View File

@ -90,7 +90,7 @@ properties:
properties:
endpoint:
$ref: /schemas/graph.yaml#/$defs/endpoint-base
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
@ -106,7 +106,6 @@ properties:
description:
If you have 1 logical lane the bridge supports routing
to either port 0 or port 1. Port 0 is suggested.
See ../../media/video-interface.txt for details.
- minItems: 2
maxItems: 2
@ -118,7 +117,6 @@ properties:
description:
If you have 2 logical lanes the bridge supports
reordering but only on physical ports 0 and 1.
See ../../media/video-interface.txt for details.
- minItems: 4
maxItems: 4
@ -132,7 +130,6 @@ properties:
description:
If you have 4 logical lanes the bridge supports
reordering in any way.
See ../../media/video-interface.txt for details.
lane-polarities:
minItems: 1
@ -141,7 +138,6 @@ properties:
enum:
- 0
- 1
description: See ../../media/video-interface.txt
dependencies:
lane-polarities: [data-lanes]

2
Documentation/devicetree/bindings/display/bridge/toshiba,tc358762.yaml
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@ -51,7 +51,7 @@ additionalProperties: false
examples:
- |
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;

35
Documentation/devicetree/bindings/display/bridge/toshiba,tc358764.txt
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@ -1,35 +0,0 @@
TC358764 MIPI-DSI to LVDS panel bridge
Required properties:
- compatible: "toshiba,tc358764"
- reg: the virtual channel number of a DSI peripheral
- vddc-supply: core voltage supply, 1.2V
- vddio-supply: I/O voltage supply, 1.8V or 3.3V
- vddlvds-supply: LVDS1/2 voltage supply, 3.3V
- reset-gpios: a GPIO spec for the reset pin
The device node can contain following 'port' child nodes,
according to the OF graph bindings defined in [1]:
0: DSI Input, not required, if the bridge is DSI controlled
1: LVDS Output, mandatory
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
bridge@0 {
reg = <0>;
compatible = "toshiba,tc358764";
vddc-supply = <&vcc_1v2_reg>;
vddio-supply = <&vcc_1v8_reg>;
vddlvds-supply = <&vcc_3v3_reg>;
reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
lvds_ep: endpoint {
remote-endpoint = <&panel_ep>;
};
};
};

89
Documentation/devicetree/bindings/display/bridge/toshiba,tc358764.yaml Normal file
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@ -0,0 +1,89 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358764.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Toshiba TC358764 MIPI-DSI to LVDS bridge
maintainers:
- Andrzej Hajda <andrzej.hajda@intel.com>
properties:
compatible:
const: toshiba,tc358764
reg:
description: Virtual channel number of a DSI peripheral
maxItems: 1
reset-gpios:
maxItems: 1
vddc-supply:
description: Core voltage supply, 1.2V
vddio-supply:
description: I/O voltage supply, 1.8V or 3.3V
vddlvds-supply:
description: LVDS1/2 voltage supply, 3.3V
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
Video port for MIPI DSI input, if the bridge DSI controlled
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
Video port for LVDS output (panel or connector).
required:
- port@1
required:
- compatible
- reg
- reset-gpios
- vddc-supply
- vddio-supply
- vddlvds-supply
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
bridge@0 {
compatible = "toshiba,tc358764";
reg = <0>;
reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>;
vddc-supply = <&vcc_1v2_reg>;
vddio-supply = <&vcc_1v8_reg>;
vddlvds-supply = <&vcc_3v3_reg>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
lvds_ep: endpoint {
remote-endpoint = <&panel_ep>;
};
};
};
};
};

2
Documentation/devicetree/bindings/display/bridge/toshiba,tc358768.yaml
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@ -87,7 +87,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;

7
Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
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@ -21,10 +21,9 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8183-disp-ccorr
- items:
- const: mediatek,mt8192-disp-ccorr
- enum:
- mediatek,mt8183-disp-ccorr
- mediatek,mt8192-disp-ccorr
- items:
- enum:
- mediatek,mt8186-disp-ccorr

10
Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
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@ -22,12 +22,10 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt2701-disp-color
- items:
- const: mediatek,mt8167-disp-color
- items:
- const: mediatek,mt8173-disp-color
- enum:
- mediatek,mt2701-disp-color
- mediatek,mt8167-disp-color
- mediatek,mt8173-disp-color
- items:
- enum:
- mediatek,mt7623-disp-color

4
Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
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@ -22,8 +22,8 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8183-disp-dither
- enum:
- mediatek,mt8183-disp-dither
- items:
- enum:
- mediatek,mt8186-disp-dither

4
Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
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@ -20,8 +20,8 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8195-disp-dsc
- enum:
- mediatek,mt8195-disp-dsc
reg:
maxItems: 1

7
Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
View File

@ -21,10 +21,9 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8173-disp-gamma
- items:
- const: mediatek,mt8183-disp-gamma
- enum:
- mediatek,mt8173-disp-gamma
- mediatek,mt8183-disp-gamma
- items:
- enum:
- mediatek,mt8186-disp-gamma

7
Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
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@ -21,10 +21,9 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8173-disp-merge
- items:
- const: mediatek,mt8195-disp-merge
- enum:
- mediatek,mt8173-disp-merge
- mediatek,mt8195-disp-merge
reg:
maxItems: 1

7
Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
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@ -21,10 +21,9 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt2712-disp-od
- items:
- const: mediatek,mt8173-disp-od
- enum:
- mediatek,mt2712-disp-od
- mediatek,mt8173-disp-od
reg:
maxItems: 1

7
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
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@ -21,10 +21,9 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8183-disp-ovl-2l
- items:
- const: mediatek,mt8192-disp-ovl-2l
- enum:
- mediatek,mt8183-disp-ovl-2l
- mediatek,mt8192-disp-ovl-2l
- items:
- enum:
- mediatek,mt8186-disp-ovl-2l

13
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
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@ -21,14 +21,11 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt2701-disp-ovl
- items:
- const: mediatek,mt8173-disp-ovl
- items:
- const: mediatek,mt8183-disp-ovl
- items:
- const: mediatek,mt8192-disp-ovl
- enum:
- mediatek,mt2701-disp-ovl
- mediatek,mt8173-disp-ovl
- mediatek,mt8183-disp-ovl
- mediatek,mt8192-disp-ovl
- items:
- enum:
- mediatek,mt7623-disp-ovl

4
Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
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@ -21,8 +21,8 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8192-disp-postmask
- enum:
- mediatek,mt8192-disp-postmask
- items:
- enum:
- mediatek,mt8186-disp-postmask

13
Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
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@ -23,14 +23,11 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt2701-disp-rdma
- items:
- const: mediatek,mt8173-disp-rdma
- items:
- const: mediatek,mt8183-disp-rdma
- items:
- const: mediatek,mt8195-disp-rdma
- enum:
- mediatek,mt2701-disp-rdma
- mediatek,mt8173-disp-rdma
- mediatek,mt8183-disp-rdma
- mediatek,mt8195-disp-rdma
- items:
- enum:
- mediatek,mt8188-disp-rdma

4
Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
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@ -21,8 +21,8 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8173-disp-split
- enum:
- mediatek,mt8173-disp-split
reg:
maxItems: 1

4
Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
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@ -22,8 +22,8 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8173-disp-ufoe
- enum:
- mediatek,mt8173-disp-ufoe
reg:
maxItems: 1

4
Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
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@ -21,8 +21,8 @@ description: |
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt8173-disp-wdma
- enum:
- mediatek,mt8173-disp-wdma
reg:
maxItems: 1

2
Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
View File

@ -61,7 +61,7 @@ properties:
- const: lut
- const: tbu
- const: tbu_rt
#MSM8996 has additional iommu clock
# MSM8996 has additional iommu clock
- items:
- const: iface
- const: bus

4
Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
View File

@ -101,6 +101,7 @@ required:
patternProperties:
"^display-controller@[1-9a-f][0-9a-f]*$":
type: object
additionalProperties: true
properties:
compatible:
contains:
@ -108,6 +109,7 @@ patternProperties:
"^dsi@[1-9a-f][0-9a-f]*$":
type: object
additionalProperties: true
properties:
compatible:
contains:
@ -115,6 +117,7 @@ patternProperties:
"^phy@[1-9a-f][0-9a-f]*$":
type: object
additionalProperties: true
properties:
compatible:
enum:
@ -132,6 +135,7 @@ patternProperties:
"^hdmi-tx@[1-9a-f][0-9a-f]*$":
type: object
additionalProperties: true
properties:
compatible:
enum:

2
Documentation/devicetree/bindings/display/panel/advantech,idk-1110wr.yaml
View File

@ -12,7 +12,7 @@ maintainers:
allOf:
- $ref: panel-common.yaml#
- $ref: /schemas/display/lvds.yaml/#
- $ref: /schemas/display/lvds.yaml#
select:
properties:

2
Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.yaml
View File

@ -12,7 +12,7 @@ maintainers:
allOf:
- $ref: panel-common.yaml#
- $ref: /schemas/display/lvds.yaml/#
- $ref: /schemas/display/lvds.yaml#
select:
properties:

2
Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml
View File

@ -12,7 +12,7 @@ maintainers:
allOf:
- $ref: panel-common.yaml#
- $ref: /schemas/display/lvds.yaml/#
- $ref: /schemas/display/lvds.yaml#
select:
properties:

2
Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.yaml
View File

@ -12,7 +12,7 @@ maintainers:
allOf:
- $ref: panel-common.yaml#
- $ref: /schemas/display/lvds.yaml/#
- $ref: /schemas/display/lvds.yaml#
select:
properties:

2
Documentation/devicetree/bindings/display/panel/nec,nl8048hl11.yaml
View File

@ -41,7 +41,7 @@ examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;

2
Documentation/devicetree/bindings/display/panel/panel-lvds.yaml
View File

@ -12,7 +12,7 @@ maintainers:
allOf:
- $ref: panel-common.yaml#
- $ref: /schemas/display/lvds.yaml/#
- $ref: /schemas/display/lvds.yaml#
select:
properties:

2
Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.yaml
View File

@ -12,7 +12,7 @@ maintainers:
allOf:
- $ref: panel-common.yaml#
- $ref: /schemas/display/lvds.yaml/#
- $ref: /schemas/display/lvds.yaml#
select:
properties:

4
Documentation/devicetree/bindings/display/panel/sharp,lq101r1sx01.yaml
View File

@ -34,8 +34,8 @@ properties:
- items:
- const: sharp,lq101r1sx03
- const: sharp,lq101r1sx01
- items:
- const: sharp,lq101r1sx01
- enum:
- sharp,lq101r1sx01
reg: true
power-supply: true

28
Documentation/devicetree/bindings/display/solomon,ssd1307fb.yaml
View File

@ -14,20 +14,18 @@ properties:
compatible:
oneOf:
# Deprecated compatible strings
- items:
- enum:
- solomon,ssd1305fb-i2c
- solomon,ssd1306fb-i2c
- solomon,ssd1307fb-i2c
- solomon,ssd1309fb-i2c
- enum:
- solomon,ssd1305fb-i2c
- solomon,ssd1306fb-i2c
- solomon,ssd1307fb-i2c
- solomon,ssd1309fb-i2c
deprecated: true
- items:
- enum:
- sinowealth,sh1106
- solomon,ssd1305
- solomon,ssd1306
- solomon,ssd1307
- solomon,ssd1309
- enum:
- sinowealth,sh1106
- solomon,ssd1305
- solomon,ssd1306
- solomon,ssd1307
- solomon,ssd1309
reg:
maxItems: 1
@ -226,7 +224,7 @@ unevaluatedProperties: false
examples:
- |
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
@ -239,7 +237,7 @@ examples:
ssd1306_i2c: oled@3d {
compatible = "solomon,ssd1306";
reg = <0x3c>;
reg = <0x3d>;
pwms = <&pwm 4 3000>;
reset-gpios = <&gpio2 7>;
solomon,com-lrremap;

2
Documentation/devicetree/bindings/eeprom/at25.yaml
View File

@ -122,7 +122,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;

2
Documentation/devicetree/bindings/example-schema.yaml
View File

@ -176,6 +176,8 @@ properties:
description: Child nodes are just another property from a json-schema
perspective.
type: object # DT nodes are json objects
# Child nodes also need additionalProperties or unevaluatedProperties
additionalProperties: false
properties:
vendor,a-child-node-property:
description: Child node properties have all the same schema

2
Documentation/devicetree/bindings/extcon/extcon-usbc-cros-ec.yaml
View File

@ -34,7 +34,7 @@ additionalProperties: false
examples:
- |
spi0 {
spi {
#address-cells = <1>;
#size-cells = <0>;
cros-ec@0 {

2
Documentation/devicetree/bindings/extcon/extcon-usbc-tusb320.yaml
View File

@ -30,7 +30,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
tusb320@61 {

54
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
View File

@ -1,54 +0,0 @@
Xilinx LogiCORE Partial Reconfig Decoupler Softcore
The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
decouplers / fpga bridges.
The controller can decouple/disable the bridges which prevents signal
changes from passing through the bridge. The controller can also
couple / enable the bridges which allows traffic to pass through the
bridge normally.
Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager
Softcore is compatible with the Xilinx LogiCORE pr-decoupler.
The Dynamic Function eXchange AXI shutdown manager prevents AXI traffic
from passing through the bridge. The controller safely handles AXI4MM
and AXI4-Lite interfaces on a Reconfigurable Partition when it is
undergoing dynamic reconfiguration, preventing the system deadlock
that can occur if AXI transactions are interrupted by DFX
The Driver supports only MMIO handling. A PR region can have multiple
PR Decouplers which can be handled independently or chained via decouple/
decouple_status signals.
Required properties:
- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
"xlnx,pr-decoupler" or
"xlnx,dfx-axi-shutdown-manager-1.00" followed by
"xlnx,dfx-axi-shutdown-manager"
- regs : base address and size for decoupler module
- clocks : input clock to IP
- clock-names : should contain "aclk"
See Documentation/devicetree/bindings/fpga/fpga-region.txt and
Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
Example:
Partial Reconfig Decoupler:
fpga-bridge@100000450 {
compatible = "xlnx,pr-decoupler-1.00",
"xlnx-pr-decoupler";
regs = <0x10000045 0x10>;
clocks = <&clkc 15>;
clock-names = "aclk";
bridge-enable = <0>;
};
Dynamic Function eXchange AXI shutdown manager:
fpga-bridge@100000450 {
compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
"xlnx,dfx-axi-shutdown-manager";
regs = <0x10000045 0x10>;
clocks = <&clkc 15>;
clock-names = "aclk";
bridge-enable = <0>;
};

51
Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
View File

@ -1,51 +0,0 @@
Xilinx Slave Serial SPI FPGA Manager
Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
bitstream over what is referred to as "slave serial" interface.
The slave serial link is not technically SPI, and might require extra
circuits in order to play nicely with other SPI slaves on the same bus.
See:
- https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
- https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
- https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
Required properties:
- compatible: should contain "xlnx,fpga-slave-serial"
- reg: spi chip select of the FPGA
- prog_b-gpios: config pin (referred to as PROGRAM_B in the manual)
- done-gpios: config status pin (referred to as DONE in the manual)
Optional properties:
- init-b-gpios: initialization status and configuration error pin
(referred to as INIT_B in the manual)
Example for full FPGA configuration:
fpga-region0 {
compatible = "fpga-region";
fpga-mgr = <&fpga_mgr_spi>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
spi1: spi@10680 {
compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
fpga_mgr_spi: fpga-mgr@0 {
compatible = "xlnx,fpga-slave-serial";
spi-max-frequency = <60000000>;
spi-cpha;
reg = <0>;
prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
init-b-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
};
};

80
Documentation/devicetree/bindings/fpga/xlnx,fpga-slave-serial.yaml Normal file
View File

@ -0,0 +1,80 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-serial.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Slave Serial SPI FPGA
maintainers:
- Nava kishore Manne <nava.kishore.manne@amd.com>
description: |
Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
over what is referred to as slave serial interface.The slave serial link is
not technically SPI, and might require extra circuits in order to play nicely
with other SPI slaves on the same bus.
Datasheets:
https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
compatible:
enum:
- xlnx,fpga-slave-serial
spi-cpha: true
spi-max-frequency:
maximum: 60000000
reg:
maxItems: 1
prog_b-gpios:
description:
config pin (referred to as PROGRAM_B in the manual)
maxItems: 1
done-gpios:
description:
config status pin (referred to as DONE in the manual)
maxItems: 1
init-b-gpios:
description:
initialization status and configuration error pin
(referred to as INIT_B in the manual)
maxItems: 1
required:
- compatible
- reg
- prog_b-gpios
- done-gpios
- init-b-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
fpga_mgr_spi: fpga-mgr@0 {
compatible = "xlnx,fpga-slave-serial";
spi-max-frequency = <60000000>;
spi-cpha;
reg = <0>;
prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
init-b-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
};
};
...

64
Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml Normal file
View File

@ -0,0 +1,64 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore
maintainers:
- Nava kishore Manne <nava.kishore.manne@amd.com>
description: |
The Xilinx LogiCORE Partial Reconfig(PR) Decoupler manages one or more
decouplers/fpga bridges. The controller can decouple/disable the bridges
which prevents signal changes from passing through the bridge. The controller
can also couple / enable the bridges which allows traffic to pass through the
bridge normally.
Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager Softcore
is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
eXchange AXI shutdown manager prevents AXI traffic from passing through the
bridge. The controller safely handles AXI4MM and AXI4-Lite interfaces on a
Reconfigurable Partition when it is undergoing dynamic reconfiguration,
preventing the system deadlock that can occur if AXI transactions are
interrupted by DFX.
Please refer to fpga-region.txt and fpga-bridge.txt in this directory for
common binding part and usage.
properties:
compatible:
oneOf:
- items:
- const: xlnx,pr-decoupler-1.00
- const: xlnx,pr-decoupler
- items:
- const: xlnx,dfx-axi-shutdown-manager-1.00
- const: xlnx,dfx-axi-shutdown-manager
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: aclk
required:
- compatible
- reg
- clocks
- clock-names
additionalProperties: false
examples:
- |
fpga-bridge@100000450 {
compatible = "xlnx,pr-decoupler-1.00", "xlnx,pr-decoupler";
reg = <0x10000045 0x10>;
clocks = <&clkc 15>;
clock-names = "aclk";
};
...

2
Documentation/devicetree/bindings/gpio/gpio-pca9570.yaml
View File

@ -34,7 +34,7 @@ additionalProperties: false
examples:
- |
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;

8
Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml
View File

@ -151,7 +151,7 @@ examples:
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
@ -177,7 +177,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c1 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
@ -203,7 +203,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c2 {
i2c {
#address-cells = <1>;
#size-cells = <0>;
@ -221,7 +221,7 @@ examples:
};
- |
i2c3 {
i2c {
#address-cells = <1>;
#size-cells = <0>;

1
Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml
View File

@ -35,6 +35,7 @@ properties:
patternProperties:
"^.*-pins?$":
$ref: /schemas/pinctrl/pinmux-node.yaml#
additionalProperties: false
properties:
pins:

1
Documentation/devicetree/bindings/hwmon/adi,ltc2992.yaml
View File

@ -32,6 +32,7 @@ properties:
patternProperties:
"^channel@([0-1])$":
type: object
additionalProperties: false
description: |
Represents the two supplies to be monitored.

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