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drm/tidss: Move reset to the end of dispc_init()

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[ Upstream commit 36d1e0852680aa038e2428d450673390111b165c ]

We do a DSS reset in the middle of the dispc_init(). While that happens
to work now, we should really make sure that e..g the fclk, which is
acquired only later in the function, is enabled when doing a reset. This
will be handled in a later patch, but for now, let's move the
dispc_softreset() call to the end of dispc_init(), which is a sensible
place for it anyway.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20231109-tidss-probe-v2-4-ac91b5ea35c0@ideasonboard.com
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Stable-dep-of: bc288a927815 ("drm/tidss: Fix dss reset")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Tomi Valkeinen 2023-11-09 09:37:57 +02:00 committed by Greg Kroah-Hartman
parent 18bd4d1846
commit d44143cdd0
1 changed files with 4 additions and 4 deletions
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8
drivers/gpu/drm/tidss/tidss_dispc.c
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@ -2777,10 +2777,6 @@ int dispc_init(struct tidss_device *tidss)
return r;
}
/* K2G display controller does not support soft reset */
if (feat->subrev != DISPC_K2G)
dispc_softreset(dispc);
for (i = 0; i < dispc->feat->num_vps; i++) {
u32 gamma_size = dispc->feat->vp_feat.color.gamma_size;
u32 *gamma_table;
@ -2829,6 +2825,10 @@ int dispc_init(struct tidss_device *tidss)
of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth",
&dispc->memory_bandwidth_limit);
/* K2G display controller does not support soft reset */
if (feat->subrev != DISPC_K2G)
dispc_softreset(dispc);
tidss->dispc = dispc;
return 0;