drm/amdgpu: revert "fix limiting AV1 to the first instance on VCN3" v3
This reverts commit 250195ff744f260c169f5427422b6f39c58cb883. The job should now be initialized when we reach the parser functions. v2: merge improved application check into this patch v3: back to the original test, but use the right ring Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1761,21 +1761,23 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = {
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.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
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};
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static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p)
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static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p,
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struct amdgpu_job *job)
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{
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struct drm_gpu_scheduler **scheds;
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/* The create msg must be in the first IB submitted */
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if (atomic_read(&p->entity->fence_seq))
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if (atomic_read(&job->base.entity->fence_seq))
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return -EINVAL;
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scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC]
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[AMDGPU_RING_PRIO_DEFAULT].sched;
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drm_sched_entity_modify_sched(p->entity, scheds, 1);
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drm_sched_entity_modify_sched(job->base.entity, scheds, 1);
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return 0;
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}
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static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr)
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static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
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uint64_t addr)
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{
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struct ttm_operation_ctx ctx = { false, false };
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struct amdgpu_bo_va_mapping *map;
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@ -1846,7 +1848,7 @@ static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr)
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if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
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continue;
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r = vcn_v3_0_limit_sched(p);
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r = vcn_v3_0_limit_sched(p, job);
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if (r)
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goto out;
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}
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@ -1860,7 +1862,7 @@ static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
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struct amdgpu_job *job,
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struct amdgpu_ib *ib)
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{
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struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
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struct amdgpu_ring *ring = amdgpu_job_ring(job);
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uint32_t msg_lo = 0, msg_hi = 0;
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unsigned i;
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int r;
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@ -1879,7 +1881,8 @@ static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
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msg_hi = val;
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} else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) &&
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val == 0) {
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r = vcn_v3_0_dec_msg(p, ((u64)msg_hi) << 32 | msg_lo);
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r = vcn_v3_0_dec_msg(p, job,
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((u64)msg_hi) << 32 | msg_lo);
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if (r)
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return r;
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}
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