drm/vc4: hdmi: Correct interlaced timings again
[ Upstream commit 771d6539f27bd55f43d8a95d53a7eeaaffa2681c ] The back porch timings were correct, only the sync offset was wrong. Correct timing is now reported for 1080i and 576i, but the h offset is incorrect for 480i for non-obvious reasons. Fixes: fb10dc451c0f ("drm/vc4: hdmi: Correct HDMI timing registers for interlaced modes") Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20221207-rpi-hvs-crtc-misc-v1-14-1f8e0770798b@cerno.tech Signed-off-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -567,11 +567,12 @@ static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
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VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
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u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
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VC5_HDMI_VERTB_VSPO) |
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VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
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VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
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interlaced,
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VC4_HDMI_VERTB_VBP));
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u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
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VC4_SET_FIELD(mode->crtc_vtotal -
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mode->crtc_vsync_end - interlaced,
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mode->crtc_vsync_end,
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VC4_HDMI_VERTB_VBP));
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HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
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