iwlwifi: trans: allow skipping scheduler hardware config
In a later patch, the hardware configuration will be moved to firmware. Prepare for this by allowing hardware configuration in the transport to be skipped by not passing a configuration on enable and passing configure_scd=false on disable. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
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0ade579cce
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@ -580,7 +580,7 @@ turn_off:
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* time, or we hadn't time to drain the AC queues.
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*/
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if (agg_state == IWL_AGG_ON)
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iwl_trans_txq_disable(priv->trans, txq_id);
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iwl_trans_txq_disable(priv->trans, txq_id, true);
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else
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IWL_DEBUG_TX_QUEUES(priv, "Don't disable tx agg: %d\n",
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agg_state);
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@ -686,7 +686,7 @@ int iwlagn_tx_agg_flush(struct iwl_priv *priv, struct ieee80211_vif *vif,
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* time, or we hadn't time to drain the AC queues.
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*/
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if (agg_state == IWL_AGG_ON)
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iwl_trans_txq_disable(priv->trans, txq_id);
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iwl_trans_txq_disable(priv->trans, txq_id, true);
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else
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IWL_DEBUG_TX_QUEUES(priv, "Don't disable tx agg: %d\n",
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agg_state);
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@ -781,7 +781,7 @@ static void iwlagn_check_ratid_empty(struct iwl_priv *priv, int sta_id, u8 tid)
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"Can continue DELBA flow ssn = next_recl = %d\n",
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tid_data->next_reclaimed);
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iwl_trans_txq_disable(priv->trans,
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tid_data->agg.txq_id);
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tid_data->agg.txq_id, true);
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iwlagn_dealloc_agg_txq(priv, tid_data->agg.txq_id);
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tid_data->agg.state = IWL_AGG_OFF;
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ieee80211_stop_tx_ba_cb_irqsafe(vif, addr, tid);
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@ -444,7 +444,9 @@ struct iwl_trans_txq_scd_cfg {
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* Must be atomic
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* @txq_enable: setup a queue. To setup an AC queue, use the
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* iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before
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* this one. The op_mode must not configure the HCMD queue. May sleep.
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* this one. The op_mode must not configure the HCMD queue. The scheduler
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* configuration may be %NULL, in which case the hardware will not be
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* configured. May sleep.
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* @txq_disable: de-configure a Tx queue to send AMPDUs
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* Must be atomic
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* @wait_tx_queue_empty: wait until tx queues are empty. May sleep.
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@ -501,7 +503,8 @@ struct iwl_trans_ops {
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void (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn,
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const struct iwl_trans_txq_scd_cfg *cfg);
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void (*txq_disable)(struct iwl_trans *trans, int queue);
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void (*txq_disable)(struct iwl_trans *trans, int queue,
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bool configure_scd);
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int (*dbgfs_register)(struct iwl_trans *trans, struct dentry* dir);
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int (*wait_tx_queue_empty)(struct iwl_trans *trans, u32 txq_bm);
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@ -773,9 +776,22 @@ static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue,
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trans->ops->reclaim(trans, queue, ssn, skbs);
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}
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static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue)
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static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue,
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bool configure_scd)
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{
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trans->ops->txq_disable(trans, queue);
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trans->ops->txq_disable(trans, queue, configure_scd);
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}
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static inline void
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iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn,
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const struct iwl_trans_txq_scd_cfg *cfg)
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{
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might_sleep();
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if (unlikely((trans->state != IWL_TRANS_FW_ALIVE)))
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IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
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trans->ops->txq_enable(trans, queue, ssn, cfg);
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}
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static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue,
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@ -789,19 +805,26 @@ static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue,
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.frame_limit = frame_limit,
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};
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might_sleep();
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if (unlikely((trans->state != IWL_TRANS_FW_ALIVE)))
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IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
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trans->ops->txq_enable(trans, queue, ssn, &cfg);
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iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg);
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}
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static inline void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue,
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int fifo)
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{
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iwl_trans_txq_enable(trans, queue, fifo, -1,
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IWL_MAX_TID_COUNT, IWL_FRAME_LIMIT, 0);
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struct iwl_trans_txq_scd_cfg cfg = {
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.fifo = fifo,
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.sta_id = -1,
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.tid = IWL_MAX_TID_COUNT,
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.frame_limit = IWL_FRAME_LIMIT,
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};
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iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg);
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}
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static inline void
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iwl_trans_txq_enable_no_scd(struct iwl_trans *trans, int queue, u16 ssn)
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{
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iwl_trans_txq_enable_cfg(trans, queue, ssn, NULL);
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}
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static inline int iwl_trans_wait_tx_queue_empty(struct iwl_trans *trans,
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@ -452,14 +452,16 @@ void iwl_mvm_mac_ctxt_release(struct iwl_mvm *mvm, struct ieee80211_vif *vif)
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switch (vif->type) {
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case NL80211_IFTYPE_P2P_DEVICE:
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iwl_trans_txq_disable(mvm->trans, IWL_MVM_OFFCHANNEL_QUEUE);
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iwl_trans_txq_disable(mvm->trans, IWL_MVM_OFFCHANNEL_QUEUE,
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true);
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break;
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case NL80211_IFTYPE_AP:
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iwl_trans_txq_disable(mvm->trans, vif->cab_queue);
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iwl_trans_txq_disable(mvm->trans, vif->cab_queue, true);
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/* fall through */
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default:
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for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
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iwl_trans_txq_disable(mvm->trans, vif->hw_queue[ac]);
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iwl_trans_txq_disable(mvm->trans, vif->hw_queue[ac],
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true);
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}
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}
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@ -910,7 +910,7 @@ int iwl_mvm_sta_tx_agg_stop(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
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}
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tid_data->ssn = 0xffff;
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iwl_trans_txq_disable(mvm->trans, txq_id);
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iwl_trans_txq_disable(mvm->trans, txq_id, true);
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/* fall through */
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case IWL_AGG_STARTING:
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case IWL_EMPTYING_HW_QUEUE_ADDBA:
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@ -965,7 +965,7 @@ int iwl_mvm_sta_tx_agg_flush(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
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if (iwl_mvm_flush_tx_path(mvm, BIT(txq_id), true))
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IWL_ERR(mvm, "Couldn't flush the AGG queue\n");
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iwl_trans_txq_disable(mvm->trans, tid_data->txq_id);
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iwl_trans_txq_disable(mvm->trans, tid_data->txq_id, true);
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}
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mvm->queue_to_mac80211[tid_data->txq_id] =
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@ -482,7 +482,7 @@ static void iwl_mvm_check_ratid_empty(struct iwl_mvm *mvm,
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IWL_DEBUG_TX_QUEUES(mvm,
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"Can continue DELBA flow ssn = next_recl = %d\n",
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tid_data->next_reclaimed);
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iwl_trans_txq_disable(mvm->trans, tid_data->txq_id);
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iwl_trans_txq_disable(mvm->trans, tid_data->txq_id, true);
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tid_data->state = IWL_AGG_OFF;
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/*
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* we can't hold the mutex - but since we are after a sequence
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@ -366,7 +366,8 @@ int iwl_pcie_tx_stop(struct iwl_trans *trans);
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void iwl_pcie_tx_free(struct iwl_trans *trans);
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void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
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const struct iwl_trans_txq_scd_cfg *cfg);
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void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue);
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void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
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bool configure_scd);
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int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
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struct iwl_device_cmd *dev_cmd, int txq_id);
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void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
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@ -1070,37 +1070,41 @@ void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
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const struct iwl_trans_txq_scd_cfg *cfg)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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u8 frame_limit = cfg->frame_limit;
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int fifo = -1;
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if (test_and_set_bit(txq_id, trans_pcie->queue_used))
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WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
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/* Stop this Tx queue before configuring it */
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iwl_scd_txq_set_inactive(trans, txq_id);
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if (cfg) {
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fifo = cfg->fifo;
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/* Set this queue as a chain-building queue unless it is CMD queue */
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if (txq_id != trans_pcie->cmd_queue)
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iwl_scd_txq_set_chain(trans, txq_id);
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/* Stop this Tx queue before configuring it */
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iwl_scd_txq_set_inactive(trans, txq_id);
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/* If this queue is mapped to a certain station: it is an AGG queue */
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if (cfg->sta_id >= 0) {
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u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
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/* Set this queue as a chain-building queue unless it is CMD */
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if (txq_id != trans_pcie->cmd_queue)
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iwl_scd_txq_set_chain(trans, txq_id);
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/* Map receiver-address / traffic-ID to this queue */
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iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
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/* If this queue is mapped to a certain station: it is an AGG */
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if (cfg->sta_id >= 0) {
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u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
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/* enable aggregations for the queue */
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iwl_scd_txq_enable_agg(trans, txq_id);
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trans_pcie->txq[txq_id].ampdu = true;
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} else {
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/*
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* disable aggregations for the queue, this will also make the
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* ra_tid mapping configuration irrelevant since it is now a
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* non-AGG queue.
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*/
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iwl_scd_txq_disable_agg(trans, txq_id);
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/* Map receiver-address / traffic-ID to this queue */
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iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
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ssn = trans_pcie->txq[txq_id].q.read_ptr;
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/* enable aggregations for the queue */
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iwl_scd_txq_enable_agg(trans, txq_id);
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trans_pcie->txq[txq_id].ampdu = true;
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} else {
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/*
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* disable aggregations for the queue, this will also
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* make the ra_tid mapping configuration irrelevant
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* since it is now a non-AGG queue.
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*/
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iwl_scd_txq_disable_agg(trans, txq_id);
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ssn = trans_pcie->txq[txq_id].q.read_ptr;
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}
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}
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/* Place first TFD at index corresponding to start sequence number.
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@ -1108,32 +1112,39 @@ void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
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trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
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trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
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iwl_write_direct32(trans, HBUS_TARG_WRPTR,
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(ssn & 0xff) | (txq_id << 8));
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iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
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if (cfg) {
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u8 frame_limit = cfg->frame_limit;
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/* Set up Tx window size and frame limit for this queue */
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iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
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SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
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iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
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iwl_write_direct32(trans, HBUS_TARG_WRPTR,
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(ssn & 0xff) | (txq_id << 8));
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iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
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/* Set up Tx window size and frame limit for this queue */
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iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
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SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
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iwl_trans_write_mem32(trans,
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trans_pcie->scd_base_addr +
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SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
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((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
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SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
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SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
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((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
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SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
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SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
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/* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
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iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
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(1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
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(cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
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(1 << SCD_QUEUE_STTS_REG_POS_WSL) |
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SCD_QUEUE_STTS_REG_MSK);
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}
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/* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
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iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
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(1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
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(cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
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(1 << SCD_QUEUE_STTS_REG_POS_WSL) |
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SCD_QUEUE_STTS_REG_MSK);
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trans_pcie->txq[txq_id].active = true;
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IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n",
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txq_id, cfg->fifo, ssn & 0xff);
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txq_id, fifo, ssn & 0xff);
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}
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void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id)
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void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
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bool configure_scd)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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u32 stts_addr = trans_pcie->scd_base_addr +
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@ -1152,10 +1163,12 @@ void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id)
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return;
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}
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iwl_scd_txq_set_inactive(trans, txq_id);
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if (configure_scd) {
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iwl_scd_txq_set_inactive(trans, txq_id);
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iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
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ARRAY_SIZE(zero_val));
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iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
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ARRAY_SIZE(zero_val));
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}
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iwl_pcie_txq_unmap(trans, txq_id);
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trans_pcie->txq[txq_id].ampdu = false;
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