drm/amd/display: Update hdcp display config
[Why] We need to update the hdcp display parameter whenever the link is updated, so the next time there is an update to hdcp we have the latest display info [How] Create a callback, and use this anytime there is a change in the link. This will be used later by the dm. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -830,6 +830,16 @@ void dc_hardware_init(struct dc *dc)
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void dc_init_callbacks(struct dc *dc,
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const struct dc_callback_init *init_params)
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{
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#ifdef CONFIG_DRM_AMD_DC_HDCP
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dc->ctx->cp_psp = init_params->cp_psp;
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#endif
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}
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void dc_deinit_callbacks(struct dc *dc)
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{
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#ifdef CONFIG_DRM_AMD_DC_HDCP
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memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
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#endif
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}
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void dc_destroy(struct dc **dc)
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@ -2690,6 +2690,24 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
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return DC_OK;
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}
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#if defined(CONFIG_DRM_AMD_DC_HDCP)
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static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
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{
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struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
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if (cp_psp && cp_psp->funcs.update_stream_config) {
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struct cp_psp_stream_config config;
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memset(&config, 0, sizeof(config));
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config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
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config.stream_enc_inst = (uint8_t) pipe_ctx->stream_res.stream_enc->id;
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config.link_enc_inst = pipe_ctx->stream->link->link_enc_hw_inst;
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config.dpms_off = dpms_off;
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config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
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cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
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}
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}
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#endif
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void core_link_enable_stream(
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struct dc_state *state,
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@ -2750,6 +2768,9 @@ void core_link_enable_stream(
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/* Do not touch link on seamless boot optimization. */
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if (pipe_ctx->stream->apply_seamless_boot_optimization) {
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pipe_ctx->stream->dpms_off = false;
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#if defined(CONFIG_DRM_AMD_DC_HDCP)
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update_psp_stream_config(pipe_ctx, false);
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#endif
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return;
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}
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@ -2757,6 +2778,9 @@ void core_link_enable_stream(
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if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
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apply_edp_fast_boot_optimization) {
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pipe_ctx->stream->dpms_off = false;
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#if defined(CONFIG_DRM_AMD_DC_HDCP)
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update_psp_stream_config(pipe_ctx, false);
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#endif
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return;
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}
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@ -2816,6 +2840,9 @@ void core_link_enable_stream(
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if (dc_is_dp_signal(pipe_ctx->stream->signal))
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enable_stream_features(pipe_ctx);
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#if defined(CONFIG_DRM_AMD_DC_HDCP)
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update_psp_stream_config(pipe_ctx, false);
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#endif
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}
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#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
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else { // if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
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@ -2833,6 +2860,10 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
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struct dc_stream_state *stream = pipe_ctx->stream;
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struct dc_link *link = stream->sink->link;
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#if defined(CONFIG_DRM_AMD_DC_HDCP)
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update_psp_stream_config(pipe_ctx, true);
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#endif
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core_dc->hwss.blank_stream(pipe_ctx);
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if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
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@ -552,7 +552,11 @@ struct dc_init_data {
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};
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struct dc_callback_init {
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#ifdef CONFIG_DRM_AMD_DC_HDCP
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struct cp_psp cp_psp;
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#else
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uint8_t reserved;
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#endif
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};
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struct dc *dc_create(const struct dc_init_data *init_params);
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@ -566,6 +570,7 @@ int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_c
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#endif
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void dc_init_callbacks(struct dc *dc,
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const struct dc_callback_init *init_params);
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void dc_deinit_callbacks(struct dc *dc);
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void dc_destroy(struct dc **dc);
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/*******************************************************************************
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@ -38,6 +38,10 @@
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#include "dal_types.h"
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#include "grph_object_defs.h"
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#ifdef CONFIG_DRM_AMD_DC_HDCP
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#include "dm_cp_psp.h"
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#endif
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/* forward declarations */
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struct dc_plane_state;
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struct dc_stream_state;
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@ -105,6 +109,9 @@ struct dc_context {
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uint32_t dc_sink_id_count;
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uint32_t dc_stream_id_count;
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uint64_t fbc_gpu_addr;
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#ifdef CONFIG_DRM_AMD_DC_HDCP
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struct cp_psp cp_psp;
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#endif
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};
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49
drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
Normal file
49
drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
Normal file
@ -0,0 +1,49 @@
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef DM_CP_PSP_IF__H
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#define DM_CP_PSP_IF__H
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struct dc_link;
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struct cp_psp_stream_config {
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uint8_t otg_inst;
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uint8_t link_enc_inst;
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uint8_t stream_enc_inst;
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void *dm_stream_ctx;
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bool dpms_off;
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};
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struct cp_psp_funcs {
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void (*update_stream_config)(void *handle, struct cp_psp_stream_config *config);
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};
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struct cp_psp {
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void *handle;
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struct cp_psp_funcs funcs;
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};
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#endif /* DM_CP_PSP_IF__H */
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@ -52,7 +52,9 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
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#include "clock_source.h"
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#include "audio.h"
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#include "dm_pp_smu.h"
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#ifdef CONFIG_DRM_AMD_DC_HDCP
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#include "dm_cp_psp.h"
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#endif
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/************ link *****************/
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struct link_init_data {
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