drm/amdgpu/jpeg5: Add support for DPG mode
Add DPG support for JPEG 5.0 Signed-off-by: Sonny Jiang <sonjiang@amd.com> Acked-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Sonny Jiang
Alex Deucher
parent
291af3f598
commit
d4b8386c86
@ -60,6 +60,37 @@
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RREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_DATA); \
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})
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#define WREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, value, indirect) \
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do { \
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WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
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regUVD_DPG_LMA_DATA, value); \
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WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
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regUVD_DPG_LMA_MASK, 0xFFFFFFFF); \
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WREG32_SOC15( \
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JPEG, GET_INST(JPEG, inst_idx), \
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regUVD_DPG_LMA_CTL, \
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(UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
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offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT | \
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indirect << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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} while (0)
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#define RREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, mask_en) \
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do { \
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WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
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regUVD_DPG_LMA_MASK, 0xFFFFFFFF); \
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WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
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regUVD_DPG_LMA_CTL, \
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(UVD_DPG_LMA_CTL__MASK_EN_MASK | \
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offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
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RREG32_SOC15(JPEG, inst_idx, regUVD_DPG_LMA_DATA); \
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} while (0)
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#define ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, offset, value, indirect) \
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do { \
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*adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = offset; \
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*adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = value; \
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} while (0)
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struct amdgpu_jpeg_reg{
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unsigned jpeg_pitch[AMDGPU_MAX_JPEG_RINGS];
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};
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@ -31,6 +31,7 @@
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#include "vcn/vcn_5_0_0_offset.h"
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#include "vcn/vcn_5_0_0_sh_mask.h"
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#include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
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#include "jpeg_v5_0_0.h"
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static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev);
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static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
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@ -137,6 +138,10 @@ static int jpeg_v5_0_0_hw_init(void *handle)
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adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
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(adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
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/* Skip ring test because pause DPG is not implemented. */
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if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG)
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return 0;
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r = amdgpu_ring_test_helper(ring);
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if (r)
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return r;
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@ -235,7 +240,7 @@ static void jpeg_v5_0_0_enable_clock_gating(struct amdgpu_device *adev)
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WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
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}
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static int jpeg_v5_0_0_disable_static_power_gating(struct amdgpu_device *adev)
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static int jpeg_v5_0_0_disable_power_gating(struct amdgpu_device *adev)
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{
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uint32_t data = 0;
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@ -248,14 +253,10 @@ static int jpeg_v5_0_0_disable_static_power_gating(struct amdgpu_device *adev)
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
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~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
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/* keep the JPEG in static PG mode */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
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~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);
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return 0;
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}
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static int jpeg_v5_0_0_enable_static_power_gating(struct amdgpu_device *adev)
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static int jpeg_v5_0_0_enable_power_gating(struct amdgpu_device *adev)
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{
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/* enable anti hang mechanism */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),
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@ -273,6 +274,121 @@ static int jpeg_v5_0_0_enable_static_power_gating(struct amdgpu_device *adev)
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return 0;
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}
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static void jpeg_engine_5_0_0_dpg_clock_gating_mode(struct amdgpu_device *adev,
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int inst_idx, uint8_t indirect)
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{
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uint32_t data = 0;
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// JPEG disable CGC
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if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
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data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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else
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data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
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data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
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if (indirect) {
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ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect);
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// Turn on All JPEG clocks
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data = 0;
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ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect);
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} else {
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WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect);
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// Turn on All JPEG clocks
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data = 0;
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WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect);
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}
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}
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/**
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* jpeg_v5_0_0_start_dpg_mode - Jpeg start with dpg mode
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*
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* @adev: amdgpu_device pointer
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* @inst_idx: instance number index
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* @indirect: indirectly write sram
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*
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* Start JPEG block with dpg mode
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*/
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static int jpeg_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
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{
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struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec;
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uint32_t reg_data = 0;
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jpeg_v5_0_0_enable_power_gating(adev);
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// enable dynamic power gating mode
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reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);
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reg_data |= UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK;
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WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data);
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if (indirect)
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adev->jpeg.inst[inst_idx].dpg_sram_curr_addr =
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(uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr;
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jpeg_engine_5_0_0_dpg_clock_gating_mode(adev, inst_idx, indirect);
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/* MJPEG global tiling registers */
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if (indirect)
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ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_DEC_GFX10_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config, indirect);
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else
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WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_DEC_GFX10_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config, 1);
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/* enable System Interrupt for JRBC */
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if (indirect)
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ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_SYS_INT_EN,
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JPEG_SYS_INT_EN__DJRBC0_MASK, indirect);
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else
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WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_SYS_INT_EN,
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JPEG_SYS_INT_EN__DJRBC0_MASK, 1);
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if (indirect) {
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/* add nop to workaround PSP size check */
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ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipUVD_NO_OP, 0, indirect);
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amdgpu_jpeg_psp_update_sram(adev, inst_idx, 0);
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}
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WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,
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ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
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VCN_JPEG_DB_CTRL__EN_MASK);
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WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_VMID, 0);
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WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
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WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
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lower_32_bits(ring->gpu_addr));
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WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
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upper_32_bits(ring->gpu_addr));
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WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_RPTR, 0);
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WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR, 0);
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WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, 0x00000002L);
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WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);
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ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR);
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return 0;
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}
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/**
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* jpeg_v5_0_0_stop_dpg_mode - Jpeg stop with dpg mode
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*
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* @adev: amdgpu_device pointer
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* @inst_idx: instance number index
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*
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* Stop JPEG block with dpg mode
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*/
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static void jpeg_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
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{
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uint32_t reg_data = 0;
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reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);
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reg_data &= ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK;
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WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data);
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}
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/**
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* jpeg_v5_0_0_start - start JPEG block
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*
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@ -288,8 +404,13 @@ static int jpeg_v5_0_0_start(struct amdgpu_device *adev)
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if (adev->pm.dpm_enabled)
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amdgpu_dpm_enable_jpeg(adev, true);
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if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) {
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r = jpeg_v5_0_0_start_dpg_mode(adev, 0, adev->jpeg.indirect_sram);
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return r;
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}
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/* disable power gating */
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r = jpeg_v5_0_0_disable_static_power_gating(adev);
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r = jpeg_v5_0_0_disable_power_gating(adev);
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if (r)
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return r;
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@ -300,7 +421,6 @@ static int jpeg_v5_0_0_start(struct amdgpu_device *adev)
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WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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/* enable JMI channel */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,
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~UVD_JMI_CNTL__SOFT_RESET_MASK);
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@ -340,17 +460,22 @@ static int jpeg_v5_0_0_stop(struct amdgpu_device *adev)
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{
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int r;
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/* reset JMI */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),
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UVD_JMI_CNTL__SOFT_RESET_MASK,
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~UVD_JMI_CNTL__SOFT_RESET_MASK);
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if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) {
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jpeg_v5_0_0_stop_dpg_mode(adev, 0);
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} else {
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jpeg_v5_0_0_enable_clock_gating(adev);
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/* reset JMI */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),
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UVD_JMI_CNTL__SOFT_RESET_MASK,
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~UVD_JMI_CNTL__SOFT_RESET_MASK);
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/* enable power gating */
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r = jpeg_v5_0_0_enable_static_power_gating(adev);
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if (r)
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return r;
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jpeg_v5_0_0_enable_clock_gating(adev);
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/* enable power gating */
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r = jpeg_v5_0_0_enable_power_gating(adev);
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if (r)
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return r;
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}
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if (adev->pm.dpm_enabled)
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amdgpu_dpm_enable_jpeg(adev, false);
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@ -24,6 +24,12 @@
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#ifndef __JPEG_V5_0_0_H__
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#define __JPEG_V5_0_0_H__
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#define vcnipJPEG_CGC_GATE 0x4160
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#define vcnipJPEG_CGC_CTRL 0x4161
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#define vcnipJPEG_SYS_INT_EN 0x4141
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#define vcnipUVD_NO_OP 0x0029
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#define vcnipJPEG_DEC_GFX10_ADDR_CONFIG 0x404A
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extern const struct amdgpu_ip_block_version jpeg_v5_0_0_ip_block;
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#endif /* __JPEG_V5_0_0_H__ */
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@ -428,6 +428,7 @@ static int soc24_common_early_init(void *handle)
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adev->pg_flags = AMD_PG_SUPPORT_VCN |
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AMD_PG_SUPPORT_JPEG |
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AMD_PG_SUPPORT_JPEG_DPG |
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AMD_PG_SUPPORT_VCN_DPG;
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adev->external_rev_id = adev->rev_id + 0x50;
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break;
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