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Renesas ARM DT updates for v5.14 (take two)

Browse Source 
- External interrupt (INTC-EX) support for the R-Car M3-W+ SoC,
   - Initial support for the new RZ/G2L SoC on the RZ/G2L SMARC EVK
     board,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-arm-dt-for-v5.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.14 (take two)

  - External interrupt (INTC-EX) support for the R-Car M3-W+ SoC,
  - Initial support for the new RZ/G2L SoC on the RZ/G2L SMARC EVK
    board,
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm-dt-for-v5.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: r9a07g044: Add SYSC node
  arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK
  arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's
  dt-bindings: clock: Add r9a07g044 CPG Clock Definitions
  arm64: dts: renesas: r8a779a0: Drop power-domains property from GIC node
  arm64: dts: renesas: r8a77961: Add INTC-EX device node
  ARM: dts: silk: Configure pull-up for SOFT_SW GPIO keys
  ARM: dts: gose: Configure pull-up for SOFT_SW GPIO keys
  ARM: dts: blanche: Configure pull-up for SOFT_SW and SW25 GPIO keys
  ARM: dts: lager: Configure pull-up for SOFT_SW GPIO keys
  arm64: dts: renesas: r8a7796[01]: Fix OPP table entry voltages
  arm64: dts: renesas: Add missing opp-suspend properties

Link: https://lore.kernel.org/r/cover.1623403796.git.geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2021-06-12 08:45:36 -07:00
commit d4dd469936
15 changed files with 362 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/boot/dts/r8a7790-lager.dts
View File

@ -81,6 +81,9 @@
keyboard {
compatible = "gpio-keys";
pinctrl-0 = <&keyboard_pins>;
pinctrl-names = "default";
one {
linux,code = <KEY_1>;
label = "SW2-1";
@ -659,6 +662,11 @@
groups = "audio_clk_a";
function = "audio_clk";
};
keyboard_pins: keyboard {
pins = "GP_1_14", "GP_1_24", "GP_1_26", "GP_1_28";
bias-pull-up;
};
};
&ether {

8
arch/arm/boot/dts/r8a7792-blanche.dts
View File

@ -112,6 +112,9 @@
keyboard {
compatible = "gpio-keys";
pinctrl-0 = <&keyboard_pins>;
pinctrl-names = "default";
key-1 {
linux,code = <KEY_1>;
label = "SW2-1";
@ -235,6 +238,11 @@
function = "du1";
};
keyboard_pins: keyboard {
pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_02";
bias-pull-up;
};
pmic_irq_pins: pmicirq {
groups = "intc_irq2";
function = "intc";

10
arch/arm/boot/dts/r8a7793-gose.dts
View File

@ -64,9 +64,12 @@
reg = <0 0x40000000 0 0x40000000>;
};
gpio-keys {
keyboard {
compatible = "gpio-keys";
pinctrl-0 = <&keyboard_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
@ -567,6 +570,11 @@
function = "audio_clk";
};
keyboard_pins: keyboard {
pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3";
bias-pull-up;
};
vin0_pins: vin0 {
groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
function = "vin0";

10
arch/arm/boot/dts/r8a7794-silk.dts
View File

@ -45,9 +45,12 @@
reg = <0 0x40000000 0 0x40000000>;
};
gpio-keys {
keyboard {
compatible = "gpio-keys";
pinctrl-0 = <&keyboard_pins>;
pinctrl-names = "default";
key-3 {
gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
@ -358,6 +361,11 @@
function = "du1";
};
keyboard_pins: keyboard {
pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12";
bias-pull-up;
};
ssi_pins: sound {
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";

2
arch/arm64/boot/dts/renesas/Makefile
View File

@ -62,3 +62,5 @@ dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb

1
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View File

@ -76,6 +76,7 @@
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
opp-suspend;
};
};

7
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View File

@ -63,18 +63,19 @@
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <820000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <820000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;

18
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View File

@ -52,18 +52,19 @@
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <820000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <820000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
@ -559,10 +560,19 @@
};
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a77961", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
/* placeholder */
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 407>;
};
tmu0: timer@e61e0000 {

1
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View File

@ -1102,7 +1102,6 @@
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
};
fcpvd0: fcp@fea10000 {

132
arch/arm64/boot/dts/renesas/r9a07g044.dtsi Normal file
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@ -0,0 +1,132 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a07g044-cpg.h>
/ {
compatible = "renesas,r9a07g044";
#address-cells = <2>;
#size-cells = <2>;
/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
};
cpu1: cpu@100 {
compatible = "arm,cortex-a55";
reg = <0x100>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
};
L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
};
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
scif0: serial@1004b800 {
compatible = "renesas,scif-r9a07g044";
reg = <0 0x1004b800 0 0x400>;
interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_CLK_SCIF0>;
status = "disabled";
};
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g044-cpg";
reg = <0 0x11010000 0 0x10000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
sysc: system-controller@11020000 {
compatible = "renesas,r9a07g044-sysc";
reg = <0 0x11020000 0 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "lpm_int", "ca55stbydone_int",
"cm33stbyr_int", "ca55_deny";
status = "disabled";
};
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x11900000 0 0x40000>,
<0x0 0x11940000 0 0x60000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
};

25
arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi Normal file
View File

@ -0,0 +1,25 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2L R9A07G044L1 SoC specific parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a07g044.dtsi"
/ {
compatible = "renesas,r9a07g044l1", "renesas,r9a07g044";
cpus {
/delete-node/ cpu-map;
/delete-node/ cpu@100;
};
timer {
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};

21
arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2L SMARC EVK board
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a07g044l2.dtsi"
#include "rzg2l-smarc.dtsi"
/ {
model = "Renesas SMARC EVK based on r9a07g044l2";
compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
};

13
arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi Normal file
View File

@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2L R9A07G044L2 SoC specific parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a07g044.dtsi"
/ {
compatible = "renesas,r9a07g044l2", "renesas,r9a07g044";
};

27
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi Normal file
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@ -0,0 +1,27 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2L SMARC EVK common parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
serial0 = &scif0;
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
};
&extal_clk {
clock-frequency = <24000000>;
};
&scif0 {
status = "okay";
};

89
include/dt-bindings/clock/r9a07g044-cpg.h Normal file
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@ -0,0 +1,89 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R9A07G044 CPG Core Clocks */
#define R9A07G044_CLK_I 0
#define R9A07G044_CLK_I2 1
#define R9A07G044_CLK_G 2
#define R9A07G044_CLK_S0 3
#define R9A07G044_CLK_S1 4
#define R9A07G044_CLK_SPI0 5
#define R9A07G044_CLK_SPI1 6
#define R9A07G044_CLK_SD0 7
#define R9A07G044_CLK_SD1 8
#define R9A07G044_CLK_M0 9
#define R9A07G044_CLK_M1 10
#define R9A07G044_CLK_M2 11
#define R9A07G044_CLK_M3 12
#define R9A07G044_CLK_M4 13
#define R9A07G044_CLK_HP 14
#define R9A07G044_CLK_TSU 15
#define R9A07G044_CLK_ZT 16
#define R9A07G044_CLK_P0 17
#define R9A07G044_CLK_P1 18
#define R9A07G044_CLK_P2 19
#define R9A07G044_CLK_AT 20
#define R9A07G044_OSCCLK 21
/* R9A07G044 Module Clocks */
#define R9A07G044_CLK_GIC600 0
#define R9A07G044_CLK_IA55 1
#define R9A07G044_CLK_SYC 2
#define R9A07G044_CLK_DMAC 3
#define R9A07G044_CLK_SYSC 4
#define R9A07G044_CLK_MTU 5
#define R9A07G044_CLK_GPT 6
#define R9A07G044_CLK_ETH0 7
#define R9A07G044_CLK_ETH1 8
#define R9A07G044_CLK_I2C0 9
#define R9A07G044_CLK_I2C1 10
#define R9A07G044_CLK_I2C2 11
#define R9A07G044_CLK_I2C3 12
#define R9A07G044_CLK_SCIF0 13
#define R9A07G044_CLK_SCIF1 14
#define R9A07G044_CLK_SCIF2 15
#define R9A07G044_CLK_SCIF3 16
#define R9A07G044_CLK_SCIF4 17
#define R9A07G044_CLK_SCI0 18
#define R9A07G044_CLK_SCI1 19
#define R9A07G044_CLK_GPIO 20
#define R9A07G044_CLK_SDHI0 21
#define R9A07G044_CLK_SDHI1 22
#define R9A07G044_CLK_USB0 23
#define R9A07G044_CLK_USB1 24
#define R9A07G044_CLK_CANFD 25
#define R9A07G044_CLK_SSI0 26
#define R9A07G044_CLK_SSI1 27
#define R9A07G044_CLK_SSI2 28
#define R9A07G044_CLK_SSI3 29
#define R9A07G044_CLK_MHU 30
#define R9A07G044_CLK_OSTM0 31
#define R9A07G044_CLK_OSTM1 32
#define R9A07G044_CLK_OSTM2 33
#define R9A07G044_CLK_WDT0 34
#define R9A07G044_CLK_WDT1 35
#define R9A07G044_CLK_WDT2 36
#define R9A07G044_CLK_WDT_PON 37
#define R9A07G044_CLK_GPU 38
#define R9A07G044_CLK_ISU 39
#define R9A07G044_CLK_H264 40
#define R9A07G044_CLK_CRU 41
#define R9A07G044_CLK_MIPI_DSI 42
#define R9A07G044_CLK_LCDC 43
#define R9A07G044_CLK_SRC 44
#define R9A07G044_CLK_RSPI0 45
#define R9A07G044_CLK_RSPI1 46
#define R9A07G044_CLK_RSPI2 47
#define R9A07G044_CLK_ADC 48
#define R9A07G044_CLK_TSU_PCLK 49
#define R9A07G044_CLK_SPI 50
#define R9A07G044_CLK_MIPI_DSI_V 51
#define R9A07G044_CLK_MIPI_DSI_PIN 52
#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */