drm/amd/pm: update smu-driver if header for smu 13.0.0 and smu 13.0.10
update smu-driver if header for smu 13.0.0 and smu 13.0.10 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -24,10 +24,10 @@
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#ifndef SMU13_DRIVER_IF_V13_0_0_H
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#define SMU13_DRIVER_IF_V13_0_0_H
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#define SMU13_0_0_DRIVER_IF_VERSION 0x32
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#define SMU13_0_0_DRIVER_IF_VERSION 0x3D
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//Increment this version if SkuTable_t or BoardTable_t change
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#define PPTABLE_VERSION 0x26
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#define PPTABLE_VERSION 0x2B
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#define NUM_GFXCLK_DPM_LEVELS 16
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#define NUM_SOCCLK_DPM_LEVELS 8
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@ -96,7 +96,7 @@
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#define FEATURE_ATHUB_MMHUB_PG_BIT 48
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#define FEATURE_SOC_PCC_BIT 49
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#define FEATURE_EDC_PWRBRK_BIT 50
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#define FEATURE_SPARE_51_BIT 51
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#define FEATURE_BOMXCO_SVI3_PROG_BIT 51
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#define FEATURE_SPARE_52_BIT 52
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#define FEATURE_SPARE_53_BIT 53
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#define FEATURE_SPARE_54_BIT 54
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@ -312,6 +312,7 @@ typedef enum {
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I2C_CONTROLLER_PROTOCOL_VR_IR35217,
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I2C_CONTROLLER_PROTOCOL_TMP_MAX31875,
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I2C_CONTROLLER_PROTOCOL_INA3221,
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I2C_CONTROLLER_PROTOCOL_TMP_MAX6604,
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I2C_CONTROLLER_PROTOCOL_COUNT,
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} I2cControllerProtocol_e;
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@ -570,6 +571,7 @@ typedef enum {
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} POWER_SOURCE_e;
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typedef enum {
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MEM_VENDOR_PLACEHOLDER0,
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MEM_VENDOR_SAMSUNG,
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MEM_VENDOR_INFINEON,
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MEM_VENDOR_ELPIDA,
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@ -579,7 +581,6 @@ typedef enum {
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MEM_VENDOR_MOSEL,
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MEM_VENDOR_WINBOND,
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MEM_VENDOR_ESMT,
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MEM_VENDOR_PLACEHOLDER0,
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MEM_VENDOR_PLACEHOLDER1,
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MEM_VENDOR_PLACEHOLDER2,
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MEM_VENDOR_PLACEHOLDER3,
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@ -812,6 +813,9 @@ typedef enum {
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#define INVALID_BOARD_GPIO 0xFF
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#define MARKETING_BASE_CLOCKS 0
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#define MARKETING_GAME_CLOCKS 1
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#define MARKETING_BOOST_CLOCKS 2
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typedef struct {
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//PLL 0
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@ -1102,10 +1106,15 @@ typedef struct {
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uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
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uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin.
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uint8_t FoptEnabled;
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uint8_t DcsSpare2[3];
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uint32_t DcsFoptM; //Tuning paramters to shift Fopt calculation
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uint32_t DcsFoptB; //Tuning paramters to shift Fopt calculation
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uint32_t DcsSpare[16];
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uint32_t DcsSpare[11];
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// UCLK section
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uint16_t ShadowFreqTableUclk[NUM_UCLK_DPM_LEVELS]; // In MHz
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uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations
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uint8_t PaddingMem[3];
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@ -1251,8 +1260,13 @@ typedef struct {
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QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT];
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QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT];
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uint16_t TemperatureLimit_Hynix; // In degrees Celsius. Memory temperature limit associated with Hynix
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uint16_t TemperatureLimit_Micron; // In degrees Celsius. Memory temperature limit associated with Micron
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uint16_t TemperatureFwCtfLimit_Hynix;
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uint16_t TemperatureFwCtfLimit_Micron;
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// SECTION: Sku Reserved
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uint32_t Spare[43];
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uint32_t Spare[41];
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// Padding for MMHUB - do not modify this
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uint32_t MmHubPadding[8];
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@ -1324,8 +1338,9 @@ typedef struct {
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// UCLK Spread Spectrum
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uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT];
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uint8_t GfxclkSpreadEnable;
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// FCLK Spread Spectrum
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uint8_t FclkSpreadPadding;
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uint8_t FclkSpreadPercent; // Q4.4
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uint16_t FclkSpreadFreq; // kHz
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@ -1450,6 +1465,8 @@ typedef struct {
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uint8_t ThrottlingPercentage[THROTTLER_COUNT];
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uint8_t VmaxThrottlingPercentage;
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uint8_t Padding1[3];
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//metrics for D3hot entry/exit and driver ARM msgs
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uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];
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@ -1469,7 +1486,7 @@ typedef struct {
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typedef struct {
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SmuMetrics_t SmuMetrics;
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uint32_t Spare[30];
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uint32_t Spare[29];
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// Padding - ignore
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uint32_t MmHubPadding[8]; // SMU internal use
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