dt-bindings: soc: samsung: Fix I2C clocks order in USI binding example
Now that HSI2C binding [1] is converted to dt-schema format, it reveals incorrect HSI2C clocks order in USI binding example: .../exynos-usi.example.dt.yaml: i2c@13820000: clock-names:0: 'hsi2c' was expected From schema: .../i2c-exynos5.yaml .../exynos-usi.example.dt.yaml: i2c@13820000: clock-names:1: 'hsi2c_pclk' was expected From schema: .../i2c-exynos5.yaml Change HSI2C clock order in USI binding example to satisfy HSI2C binding requirements and fix above warnings. [1] Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20211214170924.27998-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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@ -152,8 +152,8 @@ examples:
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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clocks = <&cmu_peri 32>, <&cmu_peri 31>;
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clocks = <&cmu_peri 31>, <&cmu_peri 32>;
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clock-names = "hsi2c_pclk", "hsi2c";
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clock-names = "hsi2c", "hsi2c_pclk";
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status = "disabled";
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status = "disabled";
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};
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};
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};
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};
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