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dt-bindings: soc: samsung: Fix I2C clocks order in USI binding example

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Now that HSI2C binding [1] is converted to dt-schema format, it reveals
incorrect HSI2C clocks order in USI binding example:

    .../exynos-usi.example.dt.yaml:
    i2c@13820000: clock-names:0: 'hsi2c' was expected
    From schema: .../i2c-exynos5.yaml

    .../exynos-usi.example.dt.yaml:
    i2c@13820000: clock-names:1: 'hsi2c_pclk' was expected
    From schema: .../i2c-exynos5.yaml

Change HSI2C clock order in USI binding example to satisfy HSI2C binding
requirements and fix above warnings.

[1] Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20211214170924.27998-1-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
This commit is contained in:
Sam Protsenko 2021-12-14 19:09:24 +02:00 committed by Krzysztof Kozlowski
parent 7836149e15
commit d56a8e9c7a
1 changed files with 2 additions and 2 deletions
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4
Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
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@ -152,8 +152,8 @@ examples:
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cmu_peri 32>, <&cmu_peri 31>;
clock-names = "hsi2c_pclk", "hsi2c";
clocks = <&cmu_peri 31>, <&cmu_peri 32>;
clock-names = "hsi2c", "hsi2c_pclk";
status = "disabled";
};
};