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drm/amd/display: add plane degamma TF driver-specific property

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Allow userspace to tell the kernel driver the input space and,
therefore, uses correct predefined transfer function (TF) to go from
encoded values to linear values.

v2:
- rename TF enum prefix from DRM_ to AMDGPU_ (Harry)
- remove HLG TF

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Co-developed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Joshua Ashton 2023-11-16 18:57:45 -01:00 committed by Alex Deucher
parent 571c2fa26a
commit d5a348d96e
4 changed files with 62 additions and 2 deletions
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5
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
View File

@ -355,6 +355,11 @@ struct amdgpu_mode_info {
* size of degamma LUT as supported by the driver (read-only).
*/
struct drm_property *plane_degamma_lut_size_property;
/**
* @plane_degamma_tf_property: Plane pre-defined transfer function to
* to go from scanout/encoded values to linear values.
*/
struct drm_property *plane_degamma_tf_property;
};
#define AMDGPU_MAX_BL_LEVEL 0xFF

19
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
View File

@ -724,6 +724,18 @@ struct amdgpu_dm_wb_connector {
extern const struct amdgpu_ip_block_version dm_ip_block;
enum amdgpu_transfer_function {
AMDGPU_TRANSFER_FUNCTION_DEFAULT,
AMDGPU_TRANSFER_FUNCTION_SRGB,
AMDGPU_TRANSFER_FUNCTION_BT709,
AMDGPU_TRANSFER_FUNCTION_PQ,
AMDGPU_TRANSFER_FUNCTION_LINEAR,
AMDGPU_TRANSFER_FUNCTION_UNITY,
AMDGPU_TRANSFER_FUNCTION_GAMMA22,
AMDGPU_TRANSFER_FUNCTION_GAMMA24,
AMDGPU_TRANSFER_FUNCTION_GAMMA26,
};
struct dm_plane_state {
struct drm_plane_state base;
struct dc_plane_state *dc_state;
@ -737,6 +749,13 @@ struct dm_plane_state {
* The blob (if not NULL) is an array of &struct drm_color_lut.
*/
struct drm_property_blob *degamma_lut;
/**
* @degamma_tf:
*
* Predefined transfer function to tell DC driver the input space to
* linearize.
*/
enum amdgpu_transfer_function degamma_tf;
};
struct dm_crtc_state {

21
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
View File

@ -85,6 +85,18 @@ void amdgpu_dm_init_color_mod(void)
}
#ifdef AMD_PRIVATE_COLOR
static const struct drm_prop_enum_list amdgpu_transfer_function_enum_list[] = {
{ AMDGPU_TRANSFER_FUNCTION_DEFAULT, "Default" },
{ AMDGPU_TRANSFER_FUNCTION_SRGB, "sRGB" },
{ AMDGPU_TRANSFER_FUNCTION_BT709, "BT.709" },
{ AMDGPU_TRANSFER_FUNCTION_PQ, "PQ (Perceptual Quantizer)" },
{ AMDGPU_TRANSFER_FUNCTION_LINEAR, "Linear" },
{ AMDGPU_TRANSFER_FUNCTION_UNITY, "Unity" },
{ AMDGPU_TRANSFER_FUNCTION_GAMMA22, "Gamma 2.2" },
{ AMDGPU_TRANSFER_FUNCTION_GAMMA24, "Gamma 2.4" },
{ AMDGPU_TRANSFER_FUNCTION_GAMMA26, "Gamma 2.6" },
};
int
amdgpu_dm_create_color_properties(struct amdgpu_device *adev)
{
@ -105,6 +117,15 @@ amdgpu_dm_create_color_properties(struct amdgpu_device *adev)
return -ENOMEM;
adev->mode_info.plane_degamma_lut_size_property = prop;
prop = drm_property_create_enum(adev_to_drm(adev),
DRM_MODE_PROP_ENUM,
"AMD_PLANE_DEGAMMA_TF",
amdgpu_transfer_function_enum_list,
ARRAY_SIZE(amdgpu_transfer_function_enum_list));
if (!prop)
return -ENOMEM;
adev->mode_info.plane_degamma_tf_property = prop;
return 0;
}
#endif

19
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
View File

@ -1337,8 +1337,11 @@ static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane)
amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
WARN_ON(amdgpu_state == NULL);
if (amdgpu_state)
__drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
if (!amdgpu_state)
return;
__drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
amdgpu_state->degamma_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;
}
static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct drm_plane *plane)
@ -1361,6 +1364,8 @@ static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct
dm_plane_state->degamma_lut =
drm_property_blob_get(old_dm_plane_state->degamma_lut);
dm_plane_state->degamma_tf = old_dm_plane_state->degamma_tf;
return &dm_plane_state->base;
}
@ -1455,6 +1460,9 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
drm_object_attach_property(&plane->base,
mode_info.plane_degamma_lut_size_property,
MAX_COLOR_LUT_ENTRIES);
drm_object_attach_property(&plane->base,
dm->adev->mode_info.plane_degamma_tf_property,
AMDGPU_TRANSFER_FUNCTION_DEFAULT);
}
}
@ -1477,6 +1485,11 @@ dm_atomic_plane_set_property(struct drm_plane *plane,
&replaced);
dm_plane_state->base.color_mgmt_changed |= replaced;
return ret;
} else if (property == adev->mode_info.plane_degamma_tf_property) {
if (dm_plane_state->degamma_tf != val) {
dm_plane_state->degamma_tf = val;
dm_plane_state->base.color_mgmt_changed = 1;
}
} else {
drm_dbg_atomic(plane->dev,
"[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n",
@ -1500,6 +1513,8 @@ dm_atomic_plane_get_property(struct drm_plane *plane,
if (property == adev->mode_info.plane_degamma_lut_property) {
*val = (dm_plane_state->degamma_lut) ?
dm_plane_state->degamma_lut->base.id : 0;
} else if (property == adev->mode_info.plane_degamma_tf_property) {
*val = dm_plane_state->degamma_tf;
} else {
return -EINVAL;
}