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habanalabs: clean MMU headers definitions

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During the MMU development the MMU header files were left with unclean
definitions:

- MMU "version specific" definitions that were left in the mmu_general
  file
- unused definitions

This patch attempts, where possible, to keep definitions that can serve
multiple MMU versions (but that are not tightly bound with specific MMU
arch) in the mmu_general header file (e.g. different definitions for
number of HOPs).

Otherwise, move MMU version specific definitions (e.g. HOPs masks and
shifts) to the specific MMU version file.

Signed-off-by: Ohad Sharabi <osharabi@habana.ai>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
This commit is contained in:
Ohad Sharabi 2021-12-08 09:06:03 +02:00 committed by Oded Gabbay
parent 9993f27de1
commit d636a932b3
6 changed files with 64 additions and 49 deletions
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8
drivers/misc/habanalabs/common/mmu/mmu_v1.c
View File

@ -269,7 +269,7 @@ static int dram_default_mapping_init(struct hl_ctx *ctx)
num_of_hop3 = prop->dram_size_for_default_page_mapping;
do_div(num_of_hop3, prop->dram_page_size);
do_div(num_of_hop3, PTE_ENTRIES_IN_HOP);
do_div(num_of_hop3, HOP_PTE_ENTRIES_512);
/* add hop1 and hop2 */
total_hops = num_of_hop3 + 2;
@ -330,7 +330,7 @@ static int dram_default_mapping_init(struct hl_ctx *ctx)
for (i = 0 ; i < num_of_hop3 ; i++) {
hop3_pte_addr = ctx->dram_default_hops[i];
for (j = 0 ; j < PTE_ENTRIES_IN_HOP ; j++) {
for (j = 0 ; j < HOP_PTE_ENTRIES_512 ; j++) {
write_final_pte(ctx, hop3_pte_addr, pte_val);
get_pte(ctx, ctx->dram_default_hops[i]);
hop3_pte_addr += HL_PTE_SIZE;
@ -369,7 +369,7 @@ static void dram_default_mapping_fini(struct hl_ctx *ctx)
num_of_hop3 = prop->dram_size_for_default_page_mapping;
do_div(num_of_hop3, prop->dram_page_size);
do_div(num_of_hop3, PTE_ENTRIES_IN_HOP);
do_div(num_of_hop3, HOP_PTE_ENTRIES_512);
hop0_addr = get_hop0_addr(ctx);
/* add hop1 and hop2 */
@ -379,7 +379,7 @@ static void dram_default_mapping_fini(struct hl_ctx *ctx)
for (i = 0 ; i < num_of_hop3 ; i++) {
hop3_pte_addr = ctx->dram_default_hops[i];
for (j = 0 ; j < PTE_ENTRIES_IN_HOP ; j++) {
for (j = 0 ; j < HOP_PTE_ENTRIES_512 ; j++) {
clear_pte(ctx, hop3_pte_addr);
put_pte(ctx, ctx->dram_default_hops[i]);
hop3_pte_addr += HL_PTE_SIZE;

24
drivers/misc/habanalabs/gaudi/gaudi.c
View File

@ -593,21 +593,21 @@ static int gaudi_set_fixed_properties(struct hl_device *hdev)
else
prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
prop->mmu_pte_size = HL_PTE_SIZE;
prop->mmu_hop_table_size = HOP_TABLE_SIZE;
prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE;
prop->mmu_hop_table_size = HOP_TABLE_SIZE_512_PTE;
prop->mmu_hop0_tables_total_size = HOP0_512_PTE_TABLES_TOTAL_SIZE;
prop->dram_page_size = PAGE_SIZE_2MB;
prop->dram_supports_virtual_memory = false;
prop->pmmu.hop0_shift = HOP0_SHIFT;
prop->pmmu.hop1_shift = HOP1_SHIFT;
prop->pmmu.hop2_shift = HOP2_SHIFT;
prop->pmmu.hop3_shift = HOP3_SHIFT;
prop->pmmu.hop4_shift = HOP4_SHIFT;
prop->pmmu.hop0_mask = HOP0_MASK;
prop->pmmu.hop1_mask = HOP1_MASK;
prop->pmmu.hop2_mask = HOP2_MASK;
prop->pmmu.hop3_mask = HOP3_MASK;
prop->pmmu.hop4_mask = HOP4_MASK;
prop->pmmu.hop0_shift = MMU_V1_1_HOP0_SHIFT;
prop->pmmu.hop1_shift = MMU_V1_1_HOP1_SHIFT;
prop->pmmu.hop2_shift = MMU_V1_1_HOP2_SHIFT;
prop->pmmu.hop3_shift = MMU_V1_1_HOP3_SHIFT;
prop->pmmu.hop4_shift = MMU_V1_1_HOP4_SHIFT;
prop->pmmu.hop0_mask = MMU_V1_1_HOP0_MASK;
prop->pmmu.hop1_mask = MMU_V1_1_HOP1_MASK;
prop->pmmu.hop2_mask = MMU_V1_1_HOP2_MASK;
prop->pmmu.hop3_mask = MMU_V1_1_HOP3_MASK;
prop->pmmu.hop4_mask = MMU_V1_1_HOP4_MASK;
prop->pmmu.start_addr = VA_HOST_SPACE_START;
prop->pmmu.end_addr =
(VA_HOST_SPACE_START + VA_HOST_SPACE_SIZE / 2) - 1;

24
drivers/misc/habanalabs/goya/goya.c
View File

@ -410,21 +410,21 @@ int goya_set_fixed_properties(struct hl_device *hdev)
else
prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
prop->mmu_pte_size = HL_PTE_SIZE;
prop->mmu_hop_table_size = HOP_TABLE_SIZE;
prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE;
prop->mmu_hop_table_size = HOP_TABLE_SIZE_512_PTE;
prop->mmu_hop0_tables_total_size = HOP0_512_PTE_TABLES_TOTAL_SIZE;
prop->dram_page_size = PAGE_SIZE_2MB;
prop->dram_supports_virtual_memory = true;
prop->dmmu.hop0_shift = HOP0_SHIFT;
prop->dmmu.hop1_shift = HOP1_SHIFT;
prop->dmmu.hop2_shift = HOP2_SHIFT;
prop->dmmu.hop3_shift = HOP3_SHIFT;
prop->dmmu.hop4_shift = HOP4_SHIFT;
prop->dmmu.hop0_mask = HOP0_MASK;
prop->dmmu.hop1_mask = HOP1_MASK;
prop->dmmu.hop2_mask = HOP2_MASK;
prop->dmmu.hop3_mask = HOP3_MASK;
prop->dmmu.hop4_mask = HOP4_MASK;
prop->dmmu.hop0_shift = MMU_V1_0_HOP0_SHIFT;
prop->dmmu.hop1_shift = MMU_V1_0_HOP1_SHIFT;
prop->dmmu.hop2_shift = MMU_V1_0_HOP2_SHIFT;
prop->dmmu.hop3_shift = MMU_V1_0_HOP3_SHIFT;
prop->dmmu.hop4_shift = MMU_V1_0_HOP4_SHIFT;
prop->dmmu.hop0_mask = MMU_V1_0_HOP0_MASK;
prop->dmmu.hop1_mask = MMU_V1_0_HOP1_MASK;
prop->dmmu.hop2_mask = MMU_V1_0_HOP2_MASK;
prop->dmmu.hop3_mask = MMU_V1_0_HOP3_MASK;
prop->dmmu.hop4_mask = MMU_V1_0_HOP4_MASK;
prop->dmmu.start_addr = VA_DDR_SPACE_START;
prop->dmmu.end_addr = VA_DDR_SPACE_END;
prop->dmmu.page_size = PAGE_SIZE_2MB;

19
drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h
View File

@ -16,27 +16,18 @@
#define PAGE_PRESENT_MASK 0x0000000000001ull
#define SWAP_OUT_MASK 0x0000000000004ull
#define LAST_MASK 0x0000000000800ull
#define HOP0_MASK 0x3000000000000ull
#define HOP1_MASK 0x0FF8000000000ull
#define HOP2_MASK 0x0007FC0000000ull
#define HOP3_MASK 0x000003FE00000ull
#define HOP4_MASK 0x00000001FF000ull
#define FLAGS_MASK 0x0000000000FFFull
#define HOP0_SHIFT 48
#define HOP1_SHIFT 39
#define HOP2_SHIFT 30
#define HOP3_SHIFT 21
#define HOP4_SHIFT 12
#define MMU_ARCH_5_HOPS 5
#define HOP_PHYS_ADDR_MASK (~FLAGS_MASK)
#define HL_PTE_SIZE sizeof(u64)
#define HOP_TABLE_SIZE PAGE_SIZE_4KB
#define PTE_ENTRIES_IN_HOP (HOP_TABLE_SIZE / HL_PTE_SIZE)
#define HOP0_TABLES_TOTAL_SIZE (HOP_TABLE_SIZE * MAX_ASID)
/* definitions for HOP with 512 PTE entries */
#define HOP_PTE_ENTRIES_512 512
#define HOP_TABLE_SIZE_512_PTE (HOP_PTE_ENTRIES_512 * HL_PTE_SIZE)
#define HOP0_512_PTE_TABLES_TOTAL_SIZE (HOP_TABLE_SIZE_512_PTE * MAX_ASID)
#define MMU_HOP0_PA43_12_SHIFT 12
#define MMU_HOP0_PA49_44_SHIFT (12 + 32)

18
drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_0.h
View File

@ -8,8 +8,20 @@
#ifndef INCLUDE_MMU_V1_0_H_
#define INCLUDE_MMU_V1_0_H_
#define MMU_HOP0_PA43_12 0x490004
#define MMU_HOP0_PA49_44 0x490008
#define MMU_ASID_BUSY 0x490000
#define MMU_V1_0_HOP0_MASK 0x3000000000000ull
#define MMU_V1_0_HOP1_MASK 0x0FF8000000000ull
#define MMU_V1_0_HOP2_MASK 0x0007FC0000000ull
#define MMU_V1_0_HOP3_MASK 0x000003FE00000ull
#define MMU_V1_0_HOP4_MASK 0x00000001FF000ull
#define MMU_V1_0_HOP0_SHIFT 48
#define MMU_V1_0_HOP1_SHIFT 39
#define MMU_V1_0_HOP2_SHIFT 30
#define MMU_V1_0_HOP3_SHIFT 21
#define MMU_V1_0_HOP4_SHIFT 12
#define MMU_HOP0_PA43_12 0x490004
#define MMU_HOP0_PA49_44 0x490008
#define MMU_ASID_BUSY 0x490000
#endif /* INCLUDE_MMU_V1_0_H_ */

20
drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_1.h
View File

@ -8,9 +8,21 @@
#ifndef INCLUDE_MMU_V1_1_H_
#define INCLUDE_MMU_V1_1_H_
#define MMU_ASID 0xC12004
#define MMU_HOP0_PA43_12 0xC12008
#define MMU_HOP0_PA49_44 0xC1200C
#define MMU_BUSY 0xC12000
#define MMU_V1_1_HOP0_MASK 0x3000000000000ull
#define MMU_V1_1_HOP1_MASK 0x0FF8000000000ull
#define MMU_V1_1_HOP2_MASK 0x0007FC0000000ull
#define MMU_V1_1_HOP3_MASK 0x000003FE00000ull
#define MMU_V1_1_HOP4_MASK 0x00000001FF000ull
#define MMU_V1_1_HOP0_SHIFT 48
#define MMU_V1_1_HOP1_SHIFT 39
#define MMU_V1_1_HOP2_SHIFT 30
#define MMU_V1_1_HOP3_SHIFT 21
#define MMU_V1_1_HOP4_SHIFT 12
#define MMU_ASID 0xC12004
#define MMU_HOP0_PA43_12 0xC12008
#define MMU_HOP0_PA49_44 0xC1200C
#define MMU_BUSY 0xC12000
#endif /* INCLUDE_MMU_V1_1_H_ */