s390/pci: use register pair instead of register asm
Reviewed-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Niklas Schnelle <schnelle@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
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@ -63,16 +63,15 @@ u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status)
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/* Refresh PCI Translations */
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static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
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{
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register u64 __addr asm("2") = addr;
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register u64 __range asm("3") = range;
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union register_pair addr_range = {.even = addr, .odd = range};
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u8 cc;
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asm volatile (
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" .insn rre,0xb9d30000,%[fn],%[addr]\n"
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" .insn rre,0xb9d30000,%[fn],%[addr_range]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [fn] "+d" (fn)
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: [addr] "d" (__addr), "d" (__range)
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: [addr_range] "d" (addr_range.pair)
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: "cc");
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*status = fn >> 24 & 0xff;
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return cc;
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@ -113,21 +112,19 @@ int __zpci_set_irq_ctrl(u16 ctl, u8 isc, union zpci_sic_iib *iib)
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/* PCI Load */
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static inline int ____pcilg(u64 *data, u64 req, u64 offset, u8 *status)
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{
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register u64 __req asm("2") = req;
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register u64 __offset asm("3") = offset;
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union register_pair req_off = {.even = req, .odd = offset};
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int cc = -ENXIO;
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u64 __data;
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asm volatile (
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" .insn rre,0xb9d20000,%[data],%[req]\n"
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" .insn rre,0xb9d20000,%[data],%[req_off]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [data] "=d" (__data), [req] "+d" (__req)
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: "d" (__offset)
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: "cc");
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*status = __req >> 24 & 0xff;
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: [cc] "+d" (cc), [data] "=d" (__data),
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[req_off] "+&d" (req_off.pair) :: "cc");
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*status = req_off.even >> 24 & 0xff;
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*data = __data;
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return cc;
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}
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@ -173,21 +170,19 @@ static inline int zpci_load_fh(u64 *data, const volatile void __iomem *addr,
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static inline int __pcilg_mio(u64 *data, u64 ioaddr, u64 len, u8 *status)
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{
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register u64 addr asm("2") = ioaddr;
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register u64 r3 asm("3") = len;
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union register_pair ioaddr_len = {.even = ioaddr, .odd = len};
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int cc = -ENXIO;
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u64 __data;
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asm volatile (
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" .insn rre,0xb9d60000,%[data],%[ioaddr]\n"
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" .insn rre,0xb9d60000,%[data],%[ioaddr_len]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [data] "=d" (__data), "+d" (r3)
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: [ioaddr] "d" (addr)
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: "cc");
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*status = r3 >> 24 & 0xff;
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: [cc] "+d" (cc), [data] "=d" (__data),
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[ioaddr_len] "+&d" (ioaddr_len.pair) :: "cc");
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*status = ioaddr_len.odd >> 24 & 0xff;
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*data = __data;
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return cc;
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}
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@ -211,20 +206,19 @@ EXPORT_SYMBOL_GPL(zpci_load);
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/* PCI Store */
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static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status)
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{
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register u64 __req asm("2") = req;
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register u64 __offset asm("3") = offset;
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union register_pair req_off = {.even = req, .odd = offset};
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int cc = -ENXIO;
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asm volatile (
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" .insn rre,0xb9d00000,%[data],%[req]\n"
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" .insn rre,0xb9d00000,%[data],%[req_off]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [req] "+d" (__req)
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: "d" (__offset), [data] "d" (data)
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: [cc] "+d" (cc), [req_off] "+&d" (req_off.pair)
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: [data] "d" (data)
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: "cc");
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*status = __req >> 24 & 0xff;
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*status = req_off.even >> 24 & 0xff;
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return cc;
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}
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@ -257,20 +251,19 @@ static inline int zpci_store_fh(const volatile void __iomem *addr, u64 data,
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static inline int __pcistg_mio(u64 data, u64 ioaddr, u64 len, u8 *status)
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{
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register u64 addr asm("2") = ioaddr;
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register u64 r3 asm("3") = len;
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union register_pair ioaddr_len = {.even = ioaddr, .odd = len};
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int cc = -ENXIO;
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asm volatile (
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" .insn rre,0xb9d40000,%[data],%[ioaddr]\n"
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" .insn rre,0xb9d40000,%[data],%[ioaddr_len]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), "+d" (r3)
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: [data] "d" (data), [ioaddr] "d" (addr)
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: "cc");
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*status = r3 >> 24 & 0xff;
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: [cc] "+d" (cc), [ioaddr_len] "+&d" (ioaddr_len.pair)
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: [data] "d" (data)
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: "cc", "memory");
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*status = ioaddr_len.odd >> 24 & 0xff;
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return cc;
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}
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@ -49,8 +49,7 @@ static inline int __pcistg_mio_inuser(
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void __iomem *ioaddr, const void __user *src,
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u64 ulen, u8 *status)
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{
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register u64 addr asm("2") = (u64 __force) ioaddr;
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register u64 len asm("3") = ulen;
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union register_pair ioaddr_len = {.even = (u64 __force)ioaddr, .odd = ulen};
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int cc = -ENXIO;
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u64 val = 0;
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u64 cnt = ulen;
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@ -68,7 +67,7 @@ static inline int __pcistg_mio_inuser(
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" aghi %[src],1\n"
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" ogr %[val],%[tmp]\n"
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" brctg %[cnt],0b\n"
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"1: .insn rre,0xb9d40000,%[val],%[ioaddr]\n"
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"1: .insn rre,0xb9d40000,%[val],%[ioaddr_len]\n"
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"2: ipm %[cc]\n"
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" srl %[cc],28\n"
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"3: sacf 768\n"
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@ -76,10 +75,9 @@ static inline int __pcistg_mio_inuser(
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:
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[src] "+a" (src), [cnt] "+d" (cnt),
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[val] "+d" (val), [tmp] "=d" (tmp),
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[len] "+d" (len), [cc] "+d" (cc),
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[ioaddr] "+a" (addr)
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[cc] "+d" (cc), [ioaddr_len] "+&d" (ioaddr_len.pair)
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:: "cc", "memory");
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*status = len >> 24 & 0xff;
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*status = ioaddr_len.odd >> 24 & 0xff;
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/* did we read everything from user memory? */
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if (!cc && cnt != 0)
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@ -195,8 +193,7 @@ static inline int __pcilg_mio_inuser(
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void __user *dst, const void __iomem *ioaddr,
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u64 ulen, u8 *status)
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{
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register u64 addr asm("2") = (u64 __force) ioaddr;
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register u64 len asm("3") = ulen;
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union register_pair ioaddr_len = {.even = (u64 __force)ioaddr, .odd = ulen};
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u64 cnt = ulen;
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int shift = ulen * 8;
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int cc = -ENXIO;
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@ -209,7 +206,7 @@ static inline int __pcilg_mio_inuser(
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*/
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asm volatile (
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" sacf 256\n"
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"0: .insn rre,0xb9d60000,%[val],%[ioaddr]\n"
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"0: .insn rre,0xb9d60000,%[val],%[ioaddr_len]\n"
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"1: ipm %[cc]\n"
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" srl %[cc],28\n"
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" ltr %[cc],%[cc]\n"
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@ -222,18 +219,17 @@ static inline int __pcilg_mio_inuser(
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"4: sacf 768\n"
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EX_TABLE(0b, 4b) EX_TABLE(1b, 4b) EX_TABLE(3b, 4b)
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:
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[cc] "+d" (cc), [val] "=d" (val), [len] "+d" (len),
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[ioaddr_len] "+&d" (ioaddr_len.pair),
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[cc] "+d" (cc), [val] "=d" (val),
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[dst] "+a" (dst), [cnt] "+d" (cnt), [tmp] "=d" (tmp),
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[shift] "+d" (shift)
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:
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[ioaddr] "a" (addr)
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: "cc", "memory");
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:: "cc", "memory");
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/* did we write everything to the user space buffer? */
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if (!cc && cnt != 0)
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cc = -EFAULT;
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*status = len >> 24 & 0xff;
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*status = ioaddr_len.odd >> 24 & 0xff;
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return cc;
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}
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