net: Add missing TST_CFG_WRITE bits around sky2_pci_write
Add missing TST_CFG_WRITE bits around sky2_pci_write*() in Optima setup routines. Without the cfg-write bits, the driver may spew endless link-up messages through qlink irq. Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2152,7 +2152,9 @@ static void sky2_qlink_intr(struct sky2_hw *hw)
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/* reset PHY Link Detect */
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phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
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sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
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sky2_link_up(sky2);
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}
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@ -3082,6 +3084,7 @@ static void sky2_reset(struct sky2_hw *hw)
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reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
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/* reset PHY Link Detect */
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
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sky2_pci_write16(hw, PSM_CONFIG_REG4,
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reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
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sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
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@ -3099,6 +3102,7 @@ static void sky2_reset(struct sky2_hw *hw)
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/* restore the PCIe Link Control register */
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sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
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}
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
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/* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
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sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
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