ARM: 5952/1: ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH Kconfig
Add ARM_L1_CACHE_SHIFT_6 to arch/arm/Kconfig to allow CPUs with L1 cache lines which are 64bytes to indicate this without having to alter the arch/arm/mm/Kconfig entry each time. Update the mm Kconfig so that ARM_L1_CACHE_SHIFT default value uses this and change OMAP3 and S5PC1XX to select ARM_L1_CACHE_SHIFT_6. Acked-by: Ben Dooks <ben-linux@fluff.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -165,6 +165,11 @@ config ARCH_MTD_XIP
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config GENERIC_HARDIRQS_NO__DO_IRQ
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def_bool y
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config ARM_L1_CACHE_SHIFT_6
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bool
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help
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Setting ARM L1 cache line size to 64 Bytes.
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if OPROFILE
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config OPROFILE_ARMV6
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@ -642,6 +647,7 @@ config ARCH_S5PC1XX
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select GENERIC_GPIO
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select HAVE_CLK
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select CPU_V7
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select ARM_L1_CACHE_SHIFT_6
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help
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Samsung S5PC1XX series based systems
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@ -779,5 +779,5 @@ config CACHE_XSC3L2
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config ARM_L1_CACHE_SHIFT
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int
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default 6 if ARCH_OMAP3 || ARCH_S5PC1XX
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default 6 if ARM_L1_CACHE_SHIFT_6
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default 5
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@ -22,6 +22,7 @@ config ARCH_OMAP3
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bool "TI OMAP3"
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select CPU_V7
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select COMMON_CLKDEV
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select ARM_L1_CACHE_SHIFT_6
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config ARCH_OMAP4
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bool "TI OMAP4"
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