soc: mediatek: PMIC wrap: Fix clock rate handling
replace chipselect extension values based on SPI clock with hardcoded SoC specific values. The PMIC wrapper has the ability of extending the chipselects by configurable amounts of time. We configured the values based on the rate of SPI clock, but this is wrong. The delays should be configured based on the internal PMIC clock that latches the values from the SPI bus to the internal PMIC registers. By default this clock is 24MHz. Other clock frequencies are for debugging only and can be removed from the driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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@ -563,45 +563,17 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
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static int pwrap_init_reg_clock(struct pmic_wrapper *wrp)
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{
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unsigned long rate_spi;
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int ck_mhz;
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rate_spi = clk_get_rate(wrp->clk_spi);
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if (rate_spi > 26000000)
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ck_mhz = 26;
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else if (rate_spi > 18000000)
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ck_mhz = 18;
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else
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ck_mhz = 0;
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switch (ck_mhz) {
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case 18:
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if (pwrap_is_mt8135(wrp))
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pwrap_writel(wrp, 0xc, PWRAP_CSHEXT);
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pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_WRITE);
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pwrap_writel(wrp, 0xc, PWRAP_CSHEXT_READ);
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pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
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pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
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break;
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case 26:
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if (pwrap_is_mt8135(wrp))
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pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
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if (pwrap_is_mt8135(wrp)) {
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pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
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pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
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pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
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pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
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pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
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break;
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case 0:
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if (pwrap_is_mt8135(wrp))
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pwrap_writel(wrp, 0xf, PWRAP_CSHEXT);
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pwrap_writel(wrp, 0xf, PWRAP_CSHEXT_WRITE);
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pwrap_writel(wrp, 0xf, PWRAP_CSHEXT_READ);
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pwrap_writel(wrp, 0xf, PWRAP_CSLEXT_START);
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pwrap_writel(wrp, 0xf, PWRAP_CSLEXT_END);
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break;
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default:
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return -EINVAL;
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} else {
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pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
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pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
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pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
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pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
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}
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return 0;
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