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drm/msm/dpu: split dpu_encoder_wait_for_event into two functions

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Stop multiplexing several events via the dpu_encoder_wait_for_event()
function. Split it into two distinct functions two allow separate
handling of those events.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/579848/
Link: https://lore.kernel.org/r/20240226-fd-dpu-debug-timeout-v4-2-51eec83dde23@linaro.org
This commit is contained in:
Dmitry Baryshkov 2024-02-26 04:28:00 +02:00
parent f1d0b196ff
commit d72a3d35b7
4 changed files with 55 additions and 49 deletions
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70
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
View File

@ -1326,7 +1326,7 @@ static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc,
trace_dpu_enc_disable(DRMID(drm_enc));
/* wait for idle */
dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
dpu_encoder_wait_for_tx_complete(drm_enc);
dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
@ -2524,10 +2524,18 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
return &dpu_enc->base;
}
int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc,
enum msm_event_wait event)
/**
* dpu_encoder_wait_for_commit_done() - Wait for encoder to flush pending state
* @drm_enc: encoder pointer
*
* Wait for hardware to have flushed the current pending changes to hardware at
* a vblank or CTL_START. Physical encoders will map this differently depending
* on the type: vid mode -> vsync_irq, cmd mode -> CTL_START.
*
* Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
*/
int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_enc)
{
int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL;
struct dpu_encoder_virt *dpu_enc = NULL;
int i, ret = 0;
@ -2541,23 +2549,47 @@ int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc,
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
switch (event) {
case MSM_ENC_COMMIT_DONE:
fn_wait = phys->ops.wait_for_commit_done;
break;
case MSM_ENC_TX_COMPLETE:
fn_wait = phys->ops.wait_for_tx_complete;
break;
default:
DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",
event);
return -EINVAL;
if (phys->ops.wait_for_commit_done) {
DPU_ATRACE_BEGIN("wait_for_commit_done");
ret = phys->ops.wait_for_commit_done(phys);
DPU_ATRACE_END("wait_for_commit_done");
if (ret)
return ret;
}
}
if (fn_wait) {
DPU_ATRACE_BEGIN("wait_for_completion_event");
ret = fn_wait(phys);
DPU_ATRACE_END("wait_for_completion_event");
return ret;
}
/**
* dpu_encoder_wait_for_tx_complete() - Wait for encoder to transfer pixels to panel
* @drm_enc: encoder pointer
*
* Wait for the hardware to transfer all the pixels to the panel. Physical
* encoders will map this differently depending on the type: vid mode -> vsync_irq,
* cmd mode -> pp_done.
*
* Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
*/
int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_enc)
{
struct dpu_encoder_virt *dpu_enc = NULL;
int i, ret = 0;
if (!drm_enc) {
DPU_ERROR("invalid encoder\n");
return -EINVAL;
}
dpu_enc = to_dpu_encoder_virt(drm_enc);
DPU_DEBUG_ENC(dpu_enc, "\n");
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
if (phys->ops.wait_for_tx_complete) {
DPU_ATRACE_BEGIN("wait_for_tx_complete");
ret = phys->ops.wait_for_tx_complete(phys);
DPU_ATRACE_END("wait_for_tx_complete");
if (ret)
return ret;
}

22
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
View File

@ -93,25 +93,9 @@ void dpu_encoder_kickoff(struct drm_encoder *encoder);
*/
int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time);
/**
* dpu_encoder_wait_for_event - Waits for encoder events
* @encoder: encoder pointer
* @event: event to wait for
* MSM_ENC_COMMIT_DONE - Wait for hardware to have flushed the current pending
* frames to hardware at a vblank or ctl_start
* Encoders will map this differently depending on the
* panel type.
* vid mode -> vsync_irq
* cmd mode -> ctl_start
* MSM_ENC_TX_COMPLETE - Wait for the hardware to transfer all the pixels to
* the panel. Encoders will map this differently
* depending on the panel type.
* vid mode -> vsync_irq
* cmd mode -> pp_done
* Returns: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
*/
int dpu_encoder_wait_for_event(struct drm_encoder *drm_encoder,
enum msm_event_wait event);
int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_encoder);
int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_encoder);
/*
* dpu_encoder_get_intf_mode - get interface mode of the given encoder

2
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
View File

@ -476,7 +476,7 @@ static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
* mode panels. This may be a no-op for command mode panels.
*/
trace_dpu_kms_wait_for_commit_done(DRMID(crtc));
ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
ret = dpu_encoder_wait_for_commit_done(encoder);
if (ret && ret != -EWOULDBLOCK) {
DPU_ERROR("wait for commit done returned %d\n", ret);
break;

10
drivers/gpu/drm/msm/msm_drv.h
View File

@ -74,16 +74,6 @@ enum msm_dsi_controller {
#define MSM_GPU_MAX_RINGS 4
#define MAX_H_TILES_PER_DISPLAY 2
/**
* enum msm_event_wait - type of HW events to wait for
* @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
* @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
*/
enum msm_event_wait {
MSM_ENC_COMMIT_DONE = 0,
MSM_ENC_TX_COMPLETE,
};
/**
* struct msm_display_topology - defines a display topology pipeline
* @num_lm: number of layer mixers used