arm64: dts: ti: k3-am65-main: Add support for sdhci1
Add support for the 2nd SDHCI controller on TI's AM654x SoCs. Although it supports upto SDR104 (100 MBps @ 200 MHz) speed mode, only enable support upto High Speed (25 MBps @ 50 MHz) for now. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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@ -259,6 +259,30 @@
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dma-coherent;
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};
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sdhci1: sdhci@4fa0000 {
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compatible = "ti,am654-sdhci-5.1";
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reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
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power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
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clock-names = "clk_ahb", "clk_xin";
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-mmc-hs = <0x0>;
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ti,otap-del-sel-sd-hs = <0x0>;
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ti,otap-del-sel-sdr12 = <0x0>;
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ti,otap-del-sel-sdr25 = <0x0>;
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ti,otap-del-sel-sdr50 = <0x8>;
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ti,otap-del-sel-sdr104 = <0x7>;
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ti,otap-del-sel-ddr50 = <0x4>;
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ti,otap-del-sel-ddr52 = <0x4>;
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ti,otap-del-sel-hs200 = <0x7>;
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ti,clkbuf-sel = <0x7>;
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ti,otap-del-sel = <0x2>;
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ti,trm-icp = <0x8>;
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dma-coherent;
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no-1-8-v;
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};
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scm_conf: scm_conf@100000 {
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compatible = "syscon", "simple-mfd";
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reg = <0 0x00100000 0 0x1c000>;
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