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Refactor A80 DE & USB and DE2 code to use dev_err_probe() helper

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Merge tag 'sunxi-clk-for-6.1-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Jernej Skrabec:

Refactor A80 DE & USB and DE2 code to use dev_err_probe() helper

* tag 'sunxi-clk-for-6.1-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: ccu-sun9i-a80-usb: Use dev_err_probe() helper
  clk: sunxi-ng: ccu-sun9i-a80-de: Use dev_err_probe() helper
  clk: sunxi-ng: sun8i-de2: Use dev_err_probe() helper
  clk: sunxi-ng: d1: Limit PLL rates to stable ranges
This commit is contained in:
Stephen Boyd 2022-09-28 16:21:13 -07:00
commit d772c9370f
4 changed files with 26 additions and 38 deletions
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8
drivers/clk/sunxi-ng/ccu-sun20i-d1.c
View File

@ -104,6 +104,8 @@ static struct ccu_nm pll_video0_4x_clk = {
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.min_rate = 252000000U,
.max_rate = 2400000000U,
.common = {
.reg = 0x040,
.hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video0-4x", osc24M,
@ -126,6 +128,8 @@ static struct ccu_nm pll_video1_4x_clk = {
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.min_rate = 252000000U,
.max_rate = 2400000000U,
.common = {
.reg = 0x048,
.hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video1-4x", osc24M,
@ -175,6 +179,8 @@ static struct ccu_nm pll_audio0_4x_clk = {
.m = _SUNXI_CCU_DIV(16, 6),
.sdm = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
0x178, BIT(31)),
.min_rate = 180000000U,
.max_rate = 3000000000U,
.common = {
.reg = 0x078,
.features = CCU_FEATURE_SIGMA_DELTA_MOD,
@ -202,6 +208,8 @@ static struct ccu_nm pll_audio1_clk = {
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1),
.min_rate = 180000000U,
.max_rate = 3000000000U,
.common = {
.reg = 0x080,
.hw.init = CLK_HW_INIT_PARENTS_DATA("pll-audio1", osc24M,

28
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
View File

@ -256,29 +256,19 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev)
return PTR_ERR(reg);
bus_clk = devm_clk_get(&pdev->dev, "bus");
if (IS_ERR(bus_clk)) {
ret = PTR_ERR(bus_clk);
if (ret != -EPROBE_DEFER)
dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret);
return ret;
}
if (IS_ERR(bus_clk))
return dev_err_probe(&pdev->dev, PTR_ERR(bus_clk),
"Couldn't get bus clk\n");
mod_clk = devm_clk_get(&pdev->dev, "mod");
if (IS_ERR(mod_clk)) {
ret = PTR_ERR(mod_clk);
if (ret != -EPROBE_DEFER)
dev_err(&pdev->dev, "Couldn't get mod clk: %d\n", ret);
return ret;
}
if (IS_ERR(mod_clk))
return dev_err_probe(&pdev->dev, PTR_ERR(mod_clk),
"Couldn't get mod clk\n");
rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(rstc)) {
ret = PTR_ERR(rstc);
if (ret != -EPROBE_DEFER)
dev_err(&pdev->dev,
"Couldn't get reset control: %d\n", ret);
return ret;
}
if (IS_ERR(rstc))
return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
"Couldn't get reset control\n");
/* The clocks need to be enabled for us to access the registers */
ret = clk_prepare_enable(bus_clk);

19
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
View File

@ -213,21 +213,14 @@ static int sun9i_a80_de_clk_probe(struct platform_device *pdev)
return PTR_ERR(reg);
bus_clk = devm_clk_get(&pdev->dev, "bus");
if (IS_ERR(bus_clk)) {
ret = PTR_ERR(bus_clk);
if (ret != -EPROBE_DEFER)
dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret);
return ret;
}
if (IS_ERR(bus_clk))
return dev_err_probe(&pdev->dev, PTR_ERR(bus_clk),
"Couldn't get bus clk\n");
rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(rstc)) {
ret = PTR_ERR(rstc);
if (ret != -EPROBE_DEFER)
dev_err(&pdev->dev,
"Couldn't get reset control: %d\n", ret);
return ret;
}
if (IS_ERR(rstc))
return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
"Couldn't get reset control\n");
/* The bus clock needs to be enabled for us to access the registers */
ret = clk_prepare_enable(bus_clk);

9
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
View File

@ -101,12 +101,9 @@ static int sun9i_a80_usb_clk_probe(struct platform_device *pdev)
return PTR_ERR(reg);
bus_clk = devm_clk_get(&pdev->dev, "bus");
if (IS_ERR(bus_clk)) {
ret = PTR_ERR(bus_clk);
if (ret != -EPROBE_DEFER)
dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret);
return ret;
}
if (IS_ERR(bus_clk))
return dev_err_probe(&pdev->dev, PTR_ERR(bus_clk),
"Couldn't get bus clk\n");
/* The bus clock needs to be enabled for us to access the registers */
ret = clk_prepare_enable(bus_clk);