drm/amdgpu: add pcie bif ras related registers
These registers will be accessed for querying ras errors. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -22,6 +22,9 @@
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#ifndef _nbio_7_4_0_SMN_HEADER
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#define _nbio_7_4_0_SMN_HEADER
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// addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk
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// base address: 0x10100000
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#define smnBIFL_RAS_CENTRAL_STATUS 0x10139040
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#define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
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#define smnCPM_CONTROL 0x11180460
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@ -53,4 +56,13 @@
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#define smnPCIE_RX_NUM_NAK 0x11180038
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#define smnPCIE_RX_NUM_NAK_GENERATED 0x1118003c
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// addressBlock: nbio_iohub_nb_misc_misc_cfgdec
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// base address: 0x13a10000
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#define smnIOHC_INTERRUPT_EOI 0x13a10120
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// addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec
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// base address: 0x13a20000
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#define smnRAS_GLOBAL_STATUS_LO 0x13a20020
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#define smnRAS_GLOBAL_STATUS_HI 0x13a20024
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#endif // _nbio_7_4_0_SMN_HEADER
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@ -48436,4 +48436,47 @@
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#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
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#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
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//IOHC_INTERRUPT_EOI
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#define IOHC_INTERRUPT_EOI__SMI_EOI__SHIFT 0x0
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#define IOHC_INTERRUPT_EOI__SCI_EOI__SHIFT 0x1
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#define IOHC_INTERRUPT_EOI__NMI_EOI__SHIFT 0x2
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#define IOHC_INTERRUPT_EOI__SMI_EOI_MASK 0x00000001L
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#define IOHC_INTERRUPT_EOI__SCI_EOI_MASK 0x00000002L
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#define IOHC_INTERRUPT_EOI__NMI_EOI_MASK 0x00000004L
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//RAS_GLOBAL_STATUS_LO
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#define RAS_GLOBAL_STATUS_LO__ParityErrCorr__SHIFT 0x0
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#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal__SHIFT 0x1
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#define RAS_GLOBAL_STATUS_LO__ParityErrFatal__SHIFT 0x2
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#define RAS_GLOBAL_STATUS_LO__ParityErrSerr__SHIFT 0x3
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#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI__SHIFT 0x6
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#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI__SHIFT 0x7
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#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI__SHIFT 0x8
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#define RAS_GLOBAL_STATUS_LO__SW_SMI__SHIFT 0x9
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#define RAS_GLOBAL_STATUS_LO__SW_SCI__SHIFT 0xa
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#define RAS_GLOBAL_STATUS_LO__SW_NMI__SHIFT 0xb
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#define RAS_GLOBAL_STATUS_LO__APML_NMI__SHIFT 0xc
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#define RAS_GLOBAL_STATUS_LO__APML_SyncFld__SHIFT 0xd
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#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI__SHIFT 0xe
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#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private__SHIFT 0xf
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#define RAS_GLOBAL_STATUS_LO__ParityErrCorr_MASK 0x00000001L
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#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal_MASK 0x00000002L
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#define RAS_GLOBAL_STATUS_LO__ParityErrFatal_MASK 0x00000004L
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#define RAS_GLOBAL_STATUS_LO__ParityErrSerr_MASK 0x00000008L
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#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI_MASK 0x00000040L
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#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI_MASK 0x00000080L
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#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI_MASK 0x00000100L
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#define RAS_GLOBAL_STATUS_LO__SW_SMI_MASK 0x00000200L
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#define RAS_GLOBAL_STATUS_LO__SW_SCI_MASK 0x00000400L
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#define RAS_GLOBAL_STATUS_LO__SW_NMI_MASK 0x00000800L
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#define RAS_GLOBAL_STATUS_LO__APML_NMI_MASK 0x00001000L
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#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_MASK 0x00002000L
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#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI_MASK 0x00004000L
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#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private_MASK 0x00008000L
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//RAS_GLOBAL_STATUS_HI
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#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr__SHIFT 0x0
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#define RAS_GLOBAL_STATUS_HI__NBIF0PortAErr__SHIFT 0x1
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#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr_MASK 0x00000001L
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#define RAS_GLOBAL_STATUS_HI__NBIF0PortAErr_MASK 0x00000002L
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#endif
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