drm/amdgpu: add ib preemption status in amdgpu_job (v2)

Add ib preemption status in amdgpu_job, so that ring level function
can detect preemption and program for resuming it.

v2: squash in fix to restore job->preamble_status back to status value (Jack)

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jack Xiao 2019-01-17 15:47:36 +08:00 committed by Alex Deucher
parent f92d5c6123
commit d8780dc71d
2 changed files with 4 additions and 0 deletions

View File

@ -209,6 +209,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
skip_preamble = ring->current_ctx == fence_ctx;
if (job && ring->funcs->emit_cntxcntl) {
status |= job->preamble_status;
status |= job->preemption_status;
amdgpu_ring_emit_cntxcntl(ring, status);
}

View File

@ -29,6 +29,8 @@
#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1)
/* bit set means context switch occured */
#define AMDGPU_HAVE_CTX_SWITCH (1 << 2)
/* bit set means IB is preempted */
#define AMDGPU_IB_PREEMPTED (1 << 3)
#define to_amdgpu_job(sched_job) \
container_of((sched_job), struct amdgpu_job, base)
@ -45,6 +47,7 @@ struct amdgpu_job {
struct amdgpu_ib *ibs;
struct dma_fence *fence; /* the hw fence */
uint32_t preamble_status;
uint32_t preemption_status;
uint32_t num_ibs;
void *owner;
bool vm_needs_flush;