ARM development updates for v6.4
Four changes for v6.4: - simplify the path to the top vmlinux - three patches to fix vfp with instrumentation enabled (eg lockdep) -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEuNNh8scc2k/wOAE+9OeQG+StrGQFAmQ5P0AACgkQ9OeQG+St rGTvmxAAmhhKurfPsTG8xNhRDd/RNDg8QczgNBvwDuAe1mzzgHagrPv4mEYYDWWl 6JdoBNIJj+6bzSKcqUHrODH1QfiSBRAzdzcsRVRyrFG9bkgcefa8r6W5U6x2jbyK qrHwG1Yb2lV6m5u9MoHPZz3FMg+ozQVLaGQvyy34VdJKj+U4fecRel8U0umBor32 kedcNGx45bxBZnQitT72Wzxn5fs57TtM5/T9qlHQaKHTQ+dy3ZI/SVwTT1swmG7o 9ITLSP0EfG+viBSeAWHbqq3OeWW1GrQDYrPVA4UmLEIPdwyYf//whfEyj4DGoZxG oocmc0FQSk3FMAOl/2ghTcrgJCK78FdTcQcYk3Fbi60SnSb4bdaNwPY6VVdnKTfa aUuaN3HPneB/8B6ruGQkuaqnpp7Szwgr3pPf/2yGXco3lvdFbC2vV7j7c7Tjvvss xr3z0aXR5Nolt7YFNb0yGNbM1Z7Hcku0mE++QPMOy+HrrM3JRFLYiXnrBmeIkvWD 02cV+4g+xu5H5Nhw/9/F29tYnQchJgtv5nvRuSEsxb93+5zn/KjZS/JvWECSH/Qb R67iwKuYcw+/a5b6wi2V0z/SCJVr998U1Jbzt6QlzB32/IdqFFqO7iYXxlDeuF9N u02E0kvKMa4UVu/iDqLaEW42RM6h9TlBWrI8mewZn5XpxVmwdiQ= =/zJK -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm Pull ARM development updates from Russell King: "Four changes for v6.4: - simplify the path to the top vmlinux - three patches to fix vfp with instrumentation enabled (eg lockdep)" * tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: 9294/2: vfp: Fix broken softirq handling with instrumentation enabled ARM: 9293/1: vfp: Pass successful return address via register R3 ARM: 9292/1: vfp: Pass thread_info pointer to vfp_support_entry ARM: 9291/1: decompressor: simplify the path to the top vmlinux
This commit is contained in:
Linus Torvalds
commit
d88867a24f
@ -107,7 +107,7 @@ ccflags-remove-$(CONFIG_FUNCTION_TRACER) += -pg
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asflags-y := -DZIMAGE
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# Supply kernel BSS size to the decompressor via a linker symbol.
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KBSS_SZ = $(shell echo $$(($$($(NM) $(obj)/../../../../vmlinux | \
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KBSS_SZ = $(shell echo $$(($$($(NM) vmlinux | \
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sed -n -e 's/^\([^ ]*\) [ABD] __bss_start$$/-0x\1/p' \
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-e 's/^\([^ ]*\) [ABD] __bss_stop$$/+0x\1/p') )) )
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LDFLAGS_vmlinux = --defsym _kernel_bss_size=$(KBSS_SZ)
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@ -244,19 +244,6 @@ THUMB( fpreg .req r7 )
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.endm
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#endif
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.macro local_bh_disable, ti, tmp
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ldr \tmp, [\ti, #TI_PREEMPT]
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add \tmp, \tmp, #SOFTIRQ_DISABLE_OFFSET
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str \tmp, [\ti, #TI_PREEMPT]
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.endm
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.macro local_bh_enable_ti, ti, tmp
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get_thread_info \ti
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ldr \tmp, [\ti, #TI_PREEMPT]
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sub \tmp, \tmp, #SOFTIRQ_DISABLE_OFFSET
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str \tmp, [\ti, #TI_PREEMPT]
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.endm
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#define USERL(l, x...) \
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9999: x; \
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.pushsection __ex_table,"a"; \
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@ -22,18 +22,7 @@
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@ IRQs enabled.
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@
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ENTRY(do_vfp)
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local_bh_disable r10, r4
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ldr r4, .LCvfp
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ldr r11, [r10, #TI_CPU] @ CPU number
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add r10, r10, #TI_VFPSTATE @ r10 = workspace
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ldr pc, [r4] @ call VFP entry point
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mov r1, r10
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mov r3, r9
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b vfp_entry
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ENDPROC(do_vfp)
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ENTRY(vfp_null_entry)
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local_bh_enable_ti r10, r4
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ret lr
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ENDPROC(vfp_null_entry)
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.align 2
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.LCvfp:
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.word vfp_vector
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@ -6,9 +6,9 @@
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* Written by Deep Blue Solutions Limited.
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*
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* This code is called from the kernel's undefined instruction trap.
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* r9 holds the return address for successful handling.
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* r1 holds the thread_info pointer
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* r3 holds the return address for successful handling.
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* lr holds the return address for unrecognised instructions.
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* r10 points at the start of the private FP workspace in the thread structure
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* sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
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*/
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#include <linux/init.h>
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@ -69,13 +69,15 @@
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@ VFP hardware support entry point.
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@
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@ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
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@ r1 = thread_info pointer
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@ r2 = PC value to resume execution after successful emulation
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@ r9 = normal "successful" return address
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@ r10 = vfp_state union
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@ r11 = CPU number
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@ r3 = normal "successful" return address
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@ lr = unrecognised instruction return address
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@ IRQs enabled.
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ENTRY(vfp_support_entry)
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ldr r11, [r1, #TI_CPU] @ CPU number
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add r10, r1, #TI_VFPSTATE @ r10 = workspace
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DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
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.fpu vfpv2
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@ -85,9 +87,9 @@ ENTRY(vfp_support_entry)
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bne look_for_VFP_exceptions @ VFP is already enabled
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DBGSTR1 "enable %x", r10
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ldr r3, vfp_current_hw_state_address
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ldr r9, vfp_current_hw_state_address
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orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set
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ldr r4, [r3, r11, lsl #2] @ vfp_current_hw_state pointer
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ldr r4, [r9, r11, lsl #2] @ vfp_current_hw_state pointer
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bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled
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cmp r4, r10 @ this thread owns the hw context?
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#ifndef CONFIG_SMP
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@ -146,7 +148,7 @@ vfp_reload_hw:
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#endif
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DBGSTR1 "load state %p", r10
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str r10, [r3, r11, lsl #2] @ update the vfp_current_hw_state pointer
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str r10, [r9, r11, lsl #2] @ update the vfp_current_hw_state pointer
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@ Load the saved state back into the VFP
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VFPFLDMIA r10, r5 @ reload the working registers while
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@ FPEXC is in a safe state
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@ -175,9 +177,12 @@ vfp_hw_state_valid:
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@ else it's one 32-bit instruction, so
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@ always subtract 4 from the following
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@ instruction address.
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local_bh_enable_ti r10, r4
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ret r9 @ we think we have handled things
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mov lr, r3 @ we think we have handled things
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local_bh_enable_and_ret:
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adr r0, .
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mov r1, #SOFTIRQ_DISABLE_OFFSET
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b __local_bh_enable_ip @ tail call
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look_for_VFP_exceptions:
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@ Check for synchronous or asynchronous exception
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@ -200,13 +205,12 @@ skip:
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@ not recognised by VFP
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DBGSTR "not VFP"
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local_bh_enable_ti r10, r4
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ret lr
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b local_bh_enable_and_ret
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process_exception:
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DBGSTR "bounce"
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mov r2, sp @ nothing stacked - regdump is at TOS
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mov lr, r9 @ setup for a return to the user code.
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mov lr, r3 @ setup for a return to the user code.
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@ Now call the C code to package up the bounce to the support code
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@ r0 holds the trigger instruction
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@ -32,10 +32,9 @@
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/*
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* Our undef handlers (in entry.S)
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*/
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asmlinkage void vfp_support_entry(void);
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asmlinkage void vfp_null_entry(void);
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asmlinkage void vfp_support_entry(u32, void *, u32, u32);
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asmlinkage void (*vfp_vector)(void) = vfp_null_entry;
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static bool have_vfp __ro_after_init;
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/*
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* Dual-use variable.
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@ -645,6 +644,25 @@ static int vfp_starting_cpu(unsigned int unused)
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return 0;
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}
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/*
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* Entered with:
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*
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* r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
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* r1 = thread_info pointer
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* r2 = PC value to resume execution after successful emulation
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* r3 = normal "successful" return address
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* lr = unrecognised instruction return address
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*/
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asmlinkage void vfp_entry(u32 trigger, struct thread_info *ti, u32 resume_pc,
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u32 resume_return_address)
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{
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if (unlikely(!have_vfp))
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return;
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local_bh_disable();
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vfp_support_entry(trigger, ti, resume_pc, resume_return_address);
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}
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#ifdef CONFIG_KERNEL_MODE_NEON
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static int vfp_kmode_exception(struct pt_regs *regs, unsigned int instr)
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@ -798,7 +816,6 @@ static int __init vfp_init(void)
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vfpsid = fmrx(FPSID);
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barrier();
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unregister_undef_hook(&vfp_detect_hook);
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vfp_vector = vfp_null_entry;
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pr_info("VFP support v0.3: ");
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if (VFP_arch) {
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@ -883,7 +900,7 @@ static int __init vfp_init(void)
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"arm/vfp:starting", vfp_starting_cpu,
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vfp_dying_cpu);
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vfp_vector = vfp_support_entry;
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have_vfp = true;
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thread_register_notifier(&vfp_notifier_block);
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vfp_pm_init();
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