drm/i915: Remove begin/finish_crtc_commit, v4.
This can all be done from the intel_update_crtc function. Split out the pipe update into a separate function, just like is done for the planes. Pull in all the changes done during fastset as well. It makes no sense for it to still exist as a separate function. Changes since v1: - Inline intel_update_pipe_config() Changes since v2: - Add comments suggested by matt. - Reorder commit_pipe_config() to remove all nesting. (Ville, Matt) - Use intel_set_pipe_src_size((). (Matt) Changes since v3: - Move atomic_update_watermarks closer to the plane calls. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191004113514.17064-7-maarten.lankhorst@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com> [mlankhorst: Replace 8 spaces with tabs in comment]
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@ -135,8 +135,6 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
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const struct intel_crtc_state *pipe_config);
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static void chv_prepare_pll(struct intel_crtc *crtc,
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const struct intel_crtc_state *pipe_config);
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static void intel_begin_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
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static void intel_finish_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
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static void intel_crtc_init_scalers(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state);
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static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
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@ -4401,45 +4399,6 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
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I915_WRITE(PIPE_CHICKEN(pipe), tmp);
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}
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static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
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const struct intel_crtc_state *new_crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
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crtc->base.mode = new_crtc_state->base.mode;
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/*
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* Update pipe size and adjust fitter if needed: the reason for this is
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* that in compute_mode_changes we check the native mode (not the pfit
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* mode) to see if we can flip rather than do a full mode set. In the
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* fastboot case, we'll flip, but if we don't update the pipesrc and
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* pfit state, we'll end up with a big fb scanned out into the wrong
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* sized surface.
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*/
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I915_WRITE(PIPESRC(crtc->pipe),
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((new_crtc_state->pipe_src_w - 1) << 16) |
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(new_crtc_state->pipe_src_h - 1));
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/* on skylake this is done by detaching scalers */
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if (INTEL_GEN(dev_priv) >= 9) {
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skl_detach_scalers(new_crtc_state);
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if (new_crtc_state->pch_pfit.enabled)
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skylake_pfit_enable(new_crtc_state);
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} else if (HAS_PCH_SPLIT(dev_priv)) {
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if (new_crtc_state->pch_pfit.enabled)
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ironlake_pfit_enable(new_crtc_state);
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else if (old_crtc_state->pch_pfit.enabled)
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ironlake_pfit_disable(old_crtc_state);
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}
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if (INTEL_GEN(dev_priv) >= 11)
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icl_set_pipe_chicken(crtc);
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}
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static void intel_fdi_normal_train(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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@ -13695,13 +13654,95 @@ u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
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return crtc->base.funcs->get_vblank_counter(&crtc->base);
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}
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void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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if (!IS_GEN(dev_priv, 2))
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intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
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if (crtc_state->has_pch_encoder) {
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enum pipe pch_transcoder =
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intel_crtc_pch_transcoder(crtc);
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intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
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}
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}
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static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
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const struct intel_crtc_state *new_crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
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crtc->base.mode = new_crtc_state->base.mode;
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/*
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* Update pipe size and adjust fitter if needed: the reason for this is
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* that in compute_mode_changes we check the native mode (not the pfit
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* mode) to see if we can flip rather than do a full mode set. In the
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* fastboot case, we'll flip, but if we don't update the pipesrc and
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* pfit state, we'll end up with a big fb scanned out into the wrong
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* sized surface.
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*/
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intel_set_pipe_src_size(new_crtc_state);
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/* on skylake this is done by detaching scalers */
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if (INTEL_GEN(dev_priv) >= 9) {
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skl_detach_scalers(new_crtc_state);
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if (new_crtc_state->pch_pfit.enabled)
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skylake_pfit_enable(new_crtc_state);
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} else if (HAS_PCH_SPLIT(dev_priv)) {
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if (new_crtc_state->pch_pfit.enabled)
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ironlake_pfit_enable(new_crtc_state);
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else if (old_crtc_state->pch_pfit.enabled)
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ironlake_pfit_disable(old_crtc_state);
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}
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if (INTEL_GEN(dev_priv) >= 11)
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icl_set_pipe_chicken(crtc);
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}
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static void commit_pipe_config(struct intel_atomic_state *state,
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struct intel_crtc_state *old_crtc_state,
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struct intel_crtc_state *new_crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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bool modeset = needs_modeset(new_crtc_state);
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/*
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* During modesets pipe configuration was programmed as the
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* CRTC was enabled.
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*/
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if (!modeset) {
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if (new_crtc_state->base.color_mgmt_changed ||
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new_crtc_state->update_pipe)
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intel_color_commit(new_crtc_state);
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if (INTEL_GEN(dev_priv) >= 9)
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skl_detach_scalers(new_crtc_state);
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if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
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bdw_set_pipemisc(new_crtc_state);
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if (new_crtc_state->update_pipe)
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intel_pipe_fastset(old_crtc_state, new_crtc_state);
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}
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if (dev_priv->display.atomic_update_watermarks)
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dev_priv->display.atomic_update_watermarks(state,
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new_crtc_state);
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}
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static void intel_update_crtc(struct intel_crtc *crtc,
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struct intel_atomic_state *state,
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struct intel_crtc_state *old_crtc_state,
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struct intel_crtc_state *new_crtc_state)
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{
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struct drm_device *dev = state->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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bool modeset = needs_modeset(new_crtc_state);
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struct intel_plane_state *new_plane_state =
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intel_atomic_get_new_plane_state(state,
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@ -13725,14 +13766,27 @@ static void intel_update_crtc(struct intel_crtc *crtc,
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else if (new_plane_state)
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intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
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intel_begin_crtc_commit(state, crtc);
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/* Perform vblank evasion around commit operation */
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intel_pipe_update_start(new_crtc_state);
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commit_pipe_config(state, old_crtc_state, new_crtc_state);
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if (INTEL_GEN(dev_priv) >= 9)
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skl_update_planes_on_crtc(state, crtc);
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else
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i9xx_update_planes_on_crtc(state, crtc);
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intel_finish_crtc_commit(state, crtc);
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intel_pipe_update_end(new_crtc_state);
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/*
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* We usually enable FIFO underrun interrupts as part of the
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* CRTC enable sequence during modesets. But when we inherit a
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* valid pipe configuration from the BIOS we need to take care
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* of enabling them on the CRTC's first fastset.
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*/
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if (new_crtc_state->update_pipe && !modeset &&
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old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
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intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
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}
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static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
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@ -14522,72 +14576,6 @@ skl_max_scale(const struct intel_crtc_state *crtc_state,
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return max_scale;
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}
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static void intel_begin_crtc_commit(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_crtc_state *old_crtc_state =
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intel_atomic_get_old_crtc_state(state, crtc);
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struct intel_crtc_state *new_crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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bool modeset = needs_modeset(new_crtc_state);
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/* Perform vblank evasion around commit operation */
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intel_pipe_update_start(new_crtc_state);
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if (modeset)
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goto out;
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if (new_crtc_state->base.color_mgmt_changed ||
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new_crtc_state->update_pipe)
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intel_color_commit(new_crtc_state);
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if (new_crtc_state->update_pipe)
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intel_update_pipe_config(old_crtc_state, new_crtc_state);
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else if (INTEL_GEN(dev_priv) >= 9)
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skl_detach_scalers(new_crtc_state);
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if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
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bdw_set_pipemisc(new_crtc_state);
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out:
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if (dev_priv->display.atomic_update_watermarks)
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dev_priv->display.atomic_update_watermarks(state,
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new_crtc_state);
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}
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void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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if (!IS_GEN(dev_priv, 2))
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intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
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if (crtc_state->has_pch_encoder) {
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enum pipe pch_transcoder =
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intel_crtc_pch_transcoder(crtc);
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intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
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}
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}
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static void intel_finish_crtc_commit(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct intel_crtc_state *old_crtc_state =
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intel_atomic_get_old_crtc_state(state, crtc);
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struct intel_crtc_state *new_crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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intel_pipe_update_end(new_crtc_state);
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if (new_crtc_state->update_pipe &&
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!needs_modeset(new_crtc_state) &&
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old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
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intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
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}
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/**
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* intel_plane_destroy - destroy a plane
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* @plane: plane to destroy
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