mfd: sta2x11-mfd: Add regmap support
Signed-off-by: Davide Ciminaghi <ciminaghi@gnudd.com> Acked-by: Alessandro Rubini <rubini@gnudd.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Davide Ciminaghi
Samuel Ortiz
parent
1950c71646
commit
d94e25535a
@ -1046,6 +1046,7 @@ config MFD_STA2X11
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bool "STA2X11 multi function device support"
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depends on STA2X11
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select MFD_CORE
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select REGMAP_MMIO
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config MFD_SYSCON
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bool "System Controller Register R/W Based on Regmap"
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@ -27,17 +27,25 @@
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/sta2x11-mfd.h>
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#include <linux/regmap.h>
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#include <asm/sta2x11.h>
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static inline int __reg_within_range(unsigned int r,
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unsigned int start,
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unsigned int end)
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{
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return ((r >= start) && (r <= end));
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}
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/* This describes STA2X11 MFD chip for us, we may have several */
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struct sta2x11_mfd {
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struct sta2x11_instance *instance;
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struct regmap *regmap[sta2x11_n_mfd_plat_devs];
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spinlock_t lock;
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struct list_head list;
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void __iomem *regs[sta2x11_n_mfd_plat_devs];
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@ -127,113 +135,21 @@ u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val,
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}
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EXPORT_SYMBOL(__sta2x11_mfd_mask);
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/* Two debugfs files, for our registers (FIXME: one instance only) */
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#define REG(regname) {.name = #regname, .offset = SCTL_ ## regname}
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static struct debugfs_reg32 sta2x11_sctl_regs[] = {
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REG(SCCTL), REG(ARMCFG), REG(SCPLLCTL), REG(SCPLLFCTRL),
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REG(SCRESFRACT), REG(SCRESCTRL1), REG(SCRESXTRL2), REG(SCPEREN0),
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REG(SCPEREN1), REG(SCPEREN2), REG(SCGRST), REG(SCPCIPMCR1),
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REG(SCPCIPMCR2), REG(SCPCIPMSR1), REG(SCPCIPMSR2), REG(SCPCIPMSR3),
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REG(SCINTREN), REG(SCRISR), REG(SCCLKSTAT0), REG(SCCLKSTAT1),
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REG(SCCLKSTAT2), REG(SCRSTSTA),
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};
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#undef REG
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/*
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* Special sta2x11-mfd regmap lock/unlock functions
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*/
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static struct debugfs_regset32 sctl_regset = {
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.regs = sta2x11_sctl_regs,
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.nregs = ARRAY_SIZE(sta2x11_sctl_regs),
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};
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static void sta2x11_regmap_lock(void *__lock)
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{
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spinlock_t *lock = __lock;
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spin_lock(lock);
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}
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#define REG(regname) {.name = #regname, .offset = regname}
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static struct debugfs_reg32 sta2x11_apbreg_regs[] = {
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REG(APBREG_BSR), REG(APBREG_PAER), REG(APBREG_PWAC), REG(APBREG_PRAC),
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REG(APBREG_PCG), REG(APBREG_PUR), REG(APBREG_EMU_PCG),
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};
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#undef REG
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static struct debugfs_regset32 apbreg_regset = {
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.regs = sta2x11_apbreg_regs,
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.nregs = ARRAY_SIZE(sta2x11_apbreg_regs),
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};
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#define REG(regname) {.name = #regname, .offset = regname}
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static struct debugfs_reg32 sta2x11_apb_soc_regs_regs[] = {
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REG(PCIE_EP1_FUNC3_0_INTR_REG), REG(PCIE_EP1_FUNC7_4_INTR_REG),
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REG(PCIE_EP2_FUNC3_0_INTR_REG), REG(PCIE_EP2_FUNC7_4_INTR_REG),
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REG(PCIE_EP3_FUNC3_0_INTR_REG), REG(PCIE_EP3_FUNC7_4_INTR_REG),
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REG(PCIE_EP4_FUNC3_0_INTR_REG), REG(PCIE_EP4_FUNC7_4_INTR_REG),
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REG(PCIE_INTR_ENABLE0_REG), REG(PCIE_INTR_ENABLE1_REG),
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REG(PCIE_EP1_FUNC_TC_REG), REG(PCIE_EP2_FUNC_TC_REG),
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REG(PCIE_EP3_FUNC_TC_REG), REG(PCIE_EP4_FUNC_TC_REG),
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REG(PCIE_EP1_FUNC_F_REG), REG(PCIE_EP2_FUNC_F_REG),
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REG(PCIE_EP3_FUNC_F_REG), REG(PCIE_EP4_FUNC_F_REG),
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REG(PCIE_PAB_AMBA_SW_RST_REG), REG(PCIE_PM_STATUS_0_PORT_0_4),
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REG(PCIE_PM_STATUS_7_0_EP1), REG(PCIE_PM_STATUS_7_0_EP2),
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REG(PCIE_PM_STATUS_7_0_EP3), REG(PCIE_PM_STATUS_7_0_EP4),
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REG(PCIE_DEV_ID_0_EP1_REG), REG(PCIE_CC_REV_ID_0_EP1_REG),
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REG(PCIE_DEV_ID_1_EP1_REG), REG(PCIE_CC_REV_ID_1_EP1_REG),
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REG(PCIE_DEV_ID_2_EP1_REG), REG(PCIE_CC_REV_ID_2_EP1_REG),
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REG(PCIE_DEV_ID_3_EP1_REG), REG(PCIE_CC_REV_ID_3_EP1_REG),
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REG(PCIE_DEV_ID_4_EP1_REG), REG(PCIE_CC_REV_ID_4_EP1_REG),
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REG(PCIE_DEV_ID_5_EP1_REG), REG(PCIE_CC_REV_ID_5_EP1_REG),
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REG(PCIE_DEV_ID_6_EP1_REG), REG(PCIE_CC_REV_ID_6_EP1_REG),
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REG(PCIE_DEV_ID_7_EP1_REG), REG(PCIE_CC_REV_ID_7_EP1_REG),
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REG(PCIE_DEV_ID_0_EP2_REG), REG(PCIE_CC_REV_ID_0_EP2_REG),
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REG(PCIE_DEV_ID_1_EP2_REG), REG(PCIE_CC_REV_ID_1_EP2_REG),
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REG(PCIE_DEV_ID_2_EP2_REG), REG(PCIE_CC_REV_ID_2_EP2_REG),
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REG(PCIE_DEV_ID_3_EP2_REG), REG(PCIE_CC_REV_ID_3_EP2_REG),
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REG(PCIE_DEV_ID_4_EP2_REG), REG(PCIE_CC_REV_ID_4_EP2_REG),
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REG(PCIE_DEV_ID_5_EP2_REG), REG(PCIE_CC_REV_ID_5_EP2_REG),
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REG(PCIE_DEV_ID_6_EP2_REG), REG(PCIE_CC_REV_ID_6_EP2_REG),
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REG(PCIE_DEV_ID_7_EP2_REG), REG(PCIE_CC_REV_ID_7_EP2_REG),
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REG(PCIE_DEV_ID_0_EP3_REG), REG(PCIE_CC_REV_ID_0_EP3_REG),
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REG(PCIE_DEV_ID_1_EP3_REG), REG(PCIE_CC_REV_ID_1_EP3_REG),
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REG(PCIE_DEV_ID_2_EP3_REG), REG(PCIE_CC_REV_ID_2_EP3_REG),
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REG(PCIE_DEV_ID_3_EP3_REG), REG(PCIE_CC_REV_ID_3_EP3_REG),
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REG(PCIE_DEV_ID_4_EP3_REG), REG(PCIE_CC_REV_ID_4_EP3_REG),
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REG(PCIE_DEV_ID_5_EP3_REG), REG(PCIE_CC_REV_ID_5_EP3_REG),
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REG(PCIE_DEV_ID_6_EP3_REG), REG(PCIE_CC_REV_ID_6_EP3_REG),
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REG(PCIE_DEV_ID_7_EP3_REG), REG(PCIE_CC_REV_ID_7_EP3_REG),
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REG(PCIE_DEV_ID_0_EP4_REG), REG(PCIE_CC_REV_ID_0_EP4_REG),
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REG(PCIE_DEV_ID_1_EP4_REG), REG(PCIE_CC_REV_ID_1_EP4_REG),
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REG(PCIE_DEV_ID_2_EP4_REG), REG(PCIE_CC_REV_ID_2_EP4_REG),
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REG(PCIE_DEV_ID_3_EP4_REG), REG(PCIE_CC_REV_ID_3_EP4_REG),
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REG(PCIE_DEV_ID_4_EP4_REG), REG(PCIE_CC_REV_ID_4_EP4_REG),
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REG(PCIE_DEV_ID_5_EP4_REG), REG(PCIE_CC_REV_ID_5_EP4_REG),
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REG(PCIE_DEV_ID_6_EP4_REG), REG(PCIE_CC_REV_ID_6_EP4_REG),
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REG(PCIE_DEV_ID_7_EP4_REG), REG(PCIE_CC_REV_ID_7_EP4_REG),
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REG(PCIE_SUBSYS_VEN_ID_REG), REG(PCIE_COMMON_CLOCK_CONFIG_0_4_0),
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REG(PCIE_MIPHYP_SSC_EN_REG), REG(PCIE_MIPHYP_ADDR_REG),
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REG(PCIE_L1_ASPM_READY_REG), REG(PCIE_EXT_CFG_RDY_REG),
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REG(PCIE_SoC_INT_ROUTER_STATUS0_REG),
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REG(PCIE_SoC_INT_ROUTER_STATUS1_REG),
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REG(PCIE_SoC_INT_ROUTER_STATUS2_REG),
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REG(PCIE_SoC_INT_ROUTER_STATUS3_REG),
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REG(DMA_IP_CTRL_REG), REG(DISP_BRIDGE_PU_PD_CTRL_REG),
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REG(VIP_PU_PD_CTRL_REG), REG(USB_MLB_PU_PD_CTRL_REG),
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REG(SDIO_PU_PD_MISCFUNC_CTRL_REG1), REG(SDIO_PU_PD_MISCFUNC_CTRL_REG2),
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REG(UART_PU_PD_CTRL_REG), REG(ARM_Lock), REG(SYS_IO_CHAR_REG1),
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REG(SYS_IO_CHAR_REG2), REG(SATA_CORE_ID_REG), REG(SATA_CTRL_REG),
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REG(I2C_HSFIX_MISC_REG), REG(SPARE2_RESERVED), REG(SPARE3_RESERVED),
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REG(MASTER_LOCK_REG), REG(SYSTEM_CONFIG_STATUS_REG),
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REG(MSP_CLK_CTRL_REG), REG(COMPENSATION_REG1), REG(COMPENSATION_REG2),
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REG(COMPENSATION_REG3), REG(TEST_CTL_REG),
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};
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#undef REG
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static struct debugfs_regset32 apb_soc_regs_regset = {
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.regs = sta2x11_apb_soc_regs_regs,
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.nregs = ARRAY_SIZE(sta2x11_apb_soc_regs_regs),
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};
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static struct dentry *sta2x11_mfd_debugfs[sta2x11_n_mfd_plat_devs];
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static struct debugfs_regset32 *sta2x11_mfd_regset[sta2x11_n_mfd_plat_devs] = {
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[sta2x11_sctl] = &sctl_regset,
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[sta2x11_apbreg] = &apbreg_regset,
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[sta2x11_apb_soc_regs] = &apb_soc_regs_regset,
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};
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static void sta2x11_regmap_unlock(void *__lock)
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{
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spinlock_t *lock = __lock;
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spin_unlock(lock);
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}
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static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = {
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[sta2x11_sctl] = "sta2x11-sctl",
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@ -241,6 +157,106 @@ static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = {
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[sta2x11_apb_soc_regs] = "sta2x11-apb-soc-regs",
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};
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static bool sta2x11_sctl_writeable_reg(struct device *dev, unsigned int reg)
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{
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return !__reg_within_range(reg, SCTL_SCPCIECSBRST, SCTL_SCRSTSTA);
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}
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static struct regmap_config sta2x11_sctl_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.lock = sta2x11_regmap_lock,
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.unlock = sta2x11_regmap_unlock,
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.max_register = SCTL_SCRSTSTA,
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.writeable_reg = sta2x11_sctl_writeable_reg,
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};
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static bool sta2x11_apbreg_readable_reg(struct device *dev, unsigned int reg)
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{
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/* Two blocks (CAN and MLB, SARAC) 0x100 bytes apart */
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if (reg >= APBREG_BSR_SARAC)
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reg -= APBREG_BSR_SARAC;
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switch (reg) {
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case APBREG_BSR:
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case APBREG_PAER:
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case APBREG_PWAC:
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case APBREG_PRAC:
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case APBREG_PCG:
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case APBREG_PUR:
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case APBREG_EMU_PCG:
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return true;
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default:
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return false;
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}
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}
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static bool sta2x11_apbreg_writeable_reg(struct device *dev, unsigned int reg)
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{
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if (reg >= APBREG_BSR_SARAC)
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reg -= APBREG_BSR_SARAC;
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if (!sta2x11_apbreg_readable_reg(dev, reg))
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return false;
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return reg != APBREG_PAER;
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}
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static struct regmap_config sta2x11_apbreg_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.lock = sta2x11_regmap_lock,
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.unlock = sta2x11_regmap_unlock,
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.max_register = APBREG_EMU_PCG_SARAC,
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.readable_reg = sta2x11_apbreg_readable_reg,
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.writeable_reg = sta2x11_apbreg_writeable_reg,
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};
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static bool sta2x11_apb_soc_regs_readable_reg(struct device *dev,
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unsigned int reg)
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{
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return reg <= PCIE_SoC_INT_ROUTER_STATUS3_REG ||
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__reg_within_range(reg, DMA_IP_CTRL_REG, SPARE3_RESERVED) ||
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__reg_within_range(reg, MASTER_LOCK_REG,
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SYSTEM_CONFIG_STATUS_REG) ||
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reg == MSP_CLK_CTRL_REG ||
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__reg_within_range(reg, COMPENSATION_REG1, TEST_CTL_REG);
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}
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static bool sta2x11_apb_soc_regs_writeable_reg(struct device *dev,
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unsigned int reg)
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{
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if (!sta2x11_apb_soc_regs_readable_reg(dev, reg))
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return false;
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switch (reg) {
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case PCIE_COMMON_CLOCK_CONFIG_0_4_0:
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case SYSTEM_CONFIG_STATUS_REG:
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case COMPENSATION_REG1:
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case PCIE_SoC_INT_ROUTER_STATUS0_REG...PCIE_SoC_INT_ROUTER_STATUS3_REG:
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case PCIE_PM_STATUS_0_PORT_0_4...PCIE_PM_STATUS_7_0_EP4:
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return false;
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default:
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return true;
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}
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}
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static struct regmap_config sta2x11_apb_soc_regs_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.lock = sta2x11_regmap_lock,
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.unlock = sta2x11_regmap_unlock,
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.max_register = TEST_CTL_REG,
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.readable_reg = sta2x11_apb_soc_regs_readable_reg,
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.writeable_reg = sta2x11_apb_soc_regs_writeable_reg,
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};
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static struct regmap_config *
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sta2x11_mfd_regmap_configs[sta2x11_n_mfd_plat_devs] = {
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[sta2x11_sctl] = &sta2x11_sctl_regmap_config,
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[sta2x11_apbreg] = &sta2x11_apbreg_regmap_config,
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[sta2x11_apb_soc_regs] = &sta2x11_apb_soc_regs_regmap_config,
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};
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/* Probe for the three platform devices */
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static int sta2x11_mfd_platform_probe(struct platform_device *dev,
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@ -250,12 +266,14 @@ static int sta2x11_mfd_platform_probe(struct platform_device *dev,
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struct sta2x11_mfd *mfd;
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struct resource *res;
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const char *name = sta2x11_mfd_names[index];
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struct debugfs_regset32 *regset = sta2x11_mfd_regset[index];
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struct regmap_config *regmap_config = sta2x11_mfd_regmap_configs[index];
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pdev = dev->dev.platform_data;
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mfd = sta2x11_mfd_find(*pdev);
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if (!mfd)
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return -ENODEV;
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if (!regmap_config)
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return -ENODEV;
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res = platform_get_resource(dev, IORESOURCE_MEM, 0);
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if (!res)
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@ -269,10 +287,16 @@ static int sta2x11_mfd_platform_probe(struct platform_device *dev,
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release_mem_region(res->start, resource_size(res));
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return -ENOMEM;
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}
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regset->base = mfd->regs[index];
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sta2x11_mfd_debugfs[index] = debugfs_create_regset32(name,
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S_IFREG | S_IRUGO,
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NULL, regset);
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regmap_config->lock_arg = &mfd->lock;
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/*
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No caching, registers could be reached both via regmap and via
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void __iomem *
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*/
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regmap_config->cache_type = REGCACHE_NONE;
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mfd->regmap[index] = devm_regmap_init_mmio(&dev->dev, mfd->regs[index],
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regmap_config);
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WARN_ON(!mfd->regmap[index]);
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return 0;
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}
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@ -246,6 +246,7 @@ u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
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#define SCTL_SCPEREN1 0x20 /* Peripheral clock enable register 1 */
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#define SCTL_SCPEREN2 0x24 /* Peripheral clock enable register 2 */
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#define SCTL_SCGRST 0x28 /* Peripheral global reset */
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#define SCTL_SCPCIECSBRST 0x2c /* PCIe PAB CSB reset status register */
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#define SCTL_SCPCIPMCR1 0x30 /* PCI power management control 1 */
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#define SCTL_SCPCIPMCR2 0x34 /* PCI power management control 2 */
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#define SCTL_SCPCIPMSR1 0x38 /* PCI power management status 1 */
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