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net: phy: mscc: do not access the MDIO bus lock directly

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This patch improves the MSCC driver by using the provided
phy_lock_mdio_bus and phy_unlock_mdio_bus helpers instead of locking and
unlocking the MDIO bus lock directly. The patch is only cosmetic but
should improve maintenance and consistency.

Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Antoine Tenart 2020-06-25 17:42:08 +02:00 committed by David S. Miller
parent b9dccf91b3
commit d9608aacd3
2 changed files with 18 additions and 18 deletions
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24
drivers/net/phy/mscc/mscc_main.c
View File

@ -1288,7 +1288,7 @@ static void vsc8584_get_base_addr(struct phy_device *phydev)
struct vsc8531_private *vsc8531 = phydev->priv;
u16 val, addr;
mutex_lock(&phydev->mdio.bus->mdio_lock);
phy_lock_mdio_bus(phydev);
__phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4);
@ -1297,7 +1297,7 @@ static void vsc8584_get_base_addr(struct phy_device *phydev)
val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
__phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
/* In the package, there are two pairs of PHYs (PHY0 + PHY2 and
* PHY1 + PHY3). The first PHY of each pair (PHY0 and PHY1) is
@ -1331,7 +1331,7 @@ static int vsc8584_config_init(struct phy_device *phydev)
phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
mutex_lock(&phydev->mdio.bus->mdio_lock);
phy_lock_mdio_bus(phydev);
/* Some parts of the init sequence are identical for every PHY in the
* package. Some parts are modifying the GPIO register bank which is a
@ -1428,7 +1428,7 @@ static int vsc8584_config_init(struct phy_device *phydev)
if (ret)
goto err;
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
ret = vsc8584_macsec_init(phydev);
if (ret)
@ -1469,7 +1469,7 @@ static int vsc8584_config_init(struct phy_device *phydev)
return 0;
err:
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
return ret;
}
@ -1755,7 +1755,7 @@ static int vsc8514_config_init(struct phy_device *phydev)
phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
mutex_lock(&phydev->mdio.bus->mdio_lock);
phy_lock_mdio_bus(phydev);
/* Some parts of the init sequence are identical for every PHY in the
* package. Some parts are modifying the GPIO register bank which is a
@ -1843,14 +1843,14 @@ static int vsc8514_config_init(struct phy_device *phydev)
reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET,
PHY_S6G_PLL_STATUS);
if (reg == 0xffffffff) {
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
return -EIO;
}
} while (time_before(jiffies, deadline) && (reg & BIT(12)));
if (reg & BIT(12)) {
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
return -ETIMEDOUT;
}
@ -1870,18 +1870,18 @@ static int vsc8514_config_init(struct phy_device *phydev)
reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET,
PHY_S6G_IB_STATUS0);
if (reg == 0xffffffff) {
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
return -EIO;
}
} while (time_before(jiffies, deadline) && !(reg & BIT(8)));
if (!(reg & BIT(8))) {
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
return -ETIMEDOUT;
}
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
ret = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
@ -1908,7 +1908,7 @@ static int vsc8514_config_init(struct phy_device *phydev)
return ret;
err:
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
return ret;
}

12
drivers/net/phy/mscc/mscc_ptp.c
View File

@ -80,7 +80,7 @@ static u32 vsc85xx_ts_read_csr(struct phy_device *phydev, enum ts_blk blk,
break;
}
mutex_lock(&phydev->mdio.bus->mdio_lock);
phy_lock_mdio_bus(phydev);
phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_1588);
@ -98,7 +98,7 @@ static u32 vsc85xx_ts_read_csr(struct phy_device *phydev, enum ts_blk blk,
phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
return val;
}
@ -130,7 +130,7 @@ static void vsc85xx_ts_write_csr(struct phy_device *phydev, enum ts_blk blk,
break;
}
mutex_lock(&phydev->mdio.bus->mdio_lock);
phy_lock_mdio_bus(phydev);
bypass = phy_ts_base_read(phydev, MSCC_PHY_BYPASS_CONTROL);
@ -154,7 +154,7 @@ static void vsc85xx_ts_write_csr(struct phy_device *phydev, enum ts_blk blk,
if (cond && upper)
phy_ts_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, bypass);
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
}
/* Pick bytes from PTP header */
@ -1273,7 +1273,7 @@ static int __vsc8584_init_ptp(struct phy_device *phydev)
u32 val;
if (!vsc8584_is_1588_input_clk_configured(phydev)) {
mutex_lock(&phydev->mdio.bus->mdio_lock);
phy_lock_mdio_bus(phydev);
/* 1588_DIFF_INPUT_CLK configuration: Use an external clock for
* the LTC, as per 3.13.29 in the VSC8584 datasheet.
@ -1285,7 +1285,7 @@ static int __vsc8584_init_ptp(struct phy_device *phydev)
phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
MSCC_PHY_PAGE_STANDARD);
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
vsc8584_set_input_clk_configured(phydev);
}