x86/numachip: Add Numachip2 APIC support
Introduce support for Numachip2 remote interrupts via detecting the right ACPI SRAT signature. Access is performed via a fixed mapping in the x86 physical address space. Signed-off-by: Daniel J Blueman <daniel@numascale.com> Acked-by: Steffen Persvold <sp@numascale.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Link: http://lkml.kernel.org/r/1442768522-19217-2-git-send-email-daniel@numascale.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Daniel J Blueman
Thomas Gleixner
parent
db1003a719
commit
d9d4dee6ce
@ -14,6 +14,7 @@
|
||||
#ifndef _ASM_X86_NUMACHIP_NUMACHIP_H
|
||||
#define _ASM_X86_NUMACHIP_NUMACHIP_H
|
||||
|
||||
extern u8 numachip_system;
|
||||
extern int __init pci_numachip_init(void);
|
||||
|
||||
#endif /* _ASM_X86_NUMACHIP_NUMACHIP_H */
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
#ifndef _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
|
||||
#define _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
|
||||
|
||||
#include <linux/smp.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#define CSR_NODE_SHIFT 16
|
||||
@ -50,4 +51,38 @@ static inline void write_lcsr(unsigned long offset, unsigned int val)
|
||||
writel(swab32(val), lcsr_address(offset));
|
||||
}
|
||||
|
||||
/*
|
||||
* On NumaChip2, local CSR space is 16MB and starts at fixed offset below 4G
|
||||
*/
|
||||
|
||||
#define NUMACHIP2_LCSR_BASE 0xf0000000UL
|
||||
#define NUMACHIP2_LCSR_SIZE 0x1000000UL
|
||||
#define NUMACHIP2_APIC_ICR 0x100000
|
||||
|
||||
static inline void __iomem *numachip2_lcsr_address(unsigned long offset)
|
||||
{
|
||||
return (void __iomem *)__va(NUMACHIP2_LCSR_BASE |
|
||||
(offset & (NUMACHIP2_LCSR_SIZE - 1)));
|
||||
}
|
||||
|
||||
static inline u32 numachip2_read32_lcsr(unsigned long offset)
|
||||
{
|
||||
return readl(numachip2_lcsr_address(offset));
|
||||
}
|
||||
|
||||
static inline u64 numachip2_read64_lcsr(unsigned long offset)
|
||||
{
|
||||
return readq(numachip2_lcsr_address(offset));
|
||||
}
|
||||
|
||||
static inline void numachip2_write32_lcsr(unsigned long offset, u32 val)
|
||||
{
|
||||
writel(val, numachip2_lcsr_address(offset));
|
||||
}
|
||||
|
||||
static inline void numachip2_write64_lcsr(unsigned long offset, u64 val)
|
||||
{
|
||||
writeq(val, numachip2_lcsr_address(offset));
|
||||
}
|
||||
|
||||
#endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */
|
||||
|
||||
@ -22,6 +22,7 @@
|
||||
|
||||
u8 numachip_system __read_mostly;
|
||||
static const struct apic apic_numachip1;
|
||||
static const struct apic apic_numachip2;
|
||||
static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly;
|
||||
|
||||
static unsigned int numachip1_get_apic_id(unsigned long x)
|
||||
@ -45,6 +46,19 @@ static unsigned long numachip1_set_apic_id(unsigned int id)
|
||||
return x;
|
||||
}
|
||||
|
||||
static unsigned int numachip2_get_apic_id(unsigned long x)
|
||||
{
|
||||
u64 mcfg;
|
||||
|
||||
rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, mcfg);
|
||||
return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24);
|
||||
}
|
||||
|
||||
static unsigned long numachip2_set_apic_id(unsigned int id)
|
||||
{
|
||||
return id << 24;
|
||||
}
|
||||
|
||||
static int numachip_apic_id_valid(int apicid)
|
||||
{
|
||||
/* Trust what bootloader passes in MADT */
|
||||
@ -66,6 +80,11 @@ static void numachip1_apic_icr_write(int apicid, unsigned int val)
|
||||
write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val);
|
||||
}
|
||||
|
||||
static void numachip2_apic_icr_write(int apicid, unsigned int val)
|
||||
{
|
||||
numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val);
|
||||
}
|
||||
|
||||
static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
|
||||
{
|
||||
numachip_apic_icr_write(phys_apicid, APIC_DM_INIT);
|
||||
@ -130,6 +149,11 @@ static int __init numachip1_probe(void)
|
||||
return apic == &apic_numachip1;
|
||||
}
|
||||
|
||||
static int __init numachip2_probe(void)
|
||||
{
|
||||
return apic == &apic_numachip2;
|
||||
}
|
||||
|
||||
static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
|
||||
{
|
||||
u64 val;
|
||||
@ -155,6 +179,13 @@ static int __init numachip_system_init(void)
|
||||
numachip_apic_icr_write = numachip1_apic_icr_write;
|
||||
x86_init.pci.arch_init = pci_numachip_init;
|
||||
break;
|
||||
case 2:
|
||||
init_extra_mapping_uc(NUMACHIP2_LCSR_BASE, NUMACHIP2_LCSR_SIZE);
|
||||
numachip_apic_icr_write = numachip2_apic_icr_write;
|
||||
|
||||
/* Use MCFG config cycles rather than locked CF8 cycles */
|
||||
raw_pci_ops = &pci_mmcfg;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
@ -176,6 +207,17 @@ static int numachip1_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int numachip2_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
|
||||
{
|
||||
if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
|
||||
(strncmp(oem_table_id, "NCONECT2", 8) != 0))
|
||||
return 0;
|
||||
|
||||
numachip_system = 2;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static const struct apic apic_numachip1 __refconst = {
|
||||
.name = "NumaConnect system",
|
||||
.probe = numachip1_probe,
|
||||
@ -226,3 +268,54 @@ static const struct apic apic_numachip1 __refconst = {
|
||||
};
|
||||
|
||||
apic_driver(apic_numachip1);
|
||||
|
||||
static const struct apic apic_numachip2 __refconst = {
|
||||
.name = "NumaConnect2 system",
|
||||
.probe = numachip2_probe,
|
||||
.acpi_madt_oem_check = numachip2_acpi_madt_oem_check,
|
||||
.apic_id_valid = numachip_apic_id_valid,
|
||||
.apic_id_registered = numachip_apic_id_registered,
|
||||
|
||||
.irq_delivery_mode = dest_Fixed,
|
||||
.irq_dest_mode = 0, /* physical */
|
||||
|
||||
.target_cpus = online_target_cpus,
|
||||
.disable_esr = 0,
|
||||
.dest_logical = 0,
|
||||
.check_apicid_used = NULL,
|
||||
|
||||
.vector_allocation_domain = default_vector_allocation_domain,
|
||||
.init_apic_ldr = flat_init_apic_ldr,
|
||||
|
||||
.ioapic_phys_id_map = NULL,
|
||||
.setup_apic_routing = NULL,
|
||||
.cpu_present_to_apicid = default_cpu_present_to_apicid,
|
||||
.apicid_to_cpu_present = NULL,
|
||||
.check_phys_apicid_present = default_check_phys_apicid_present,
|
||||
.phys_pkg_id = numachip_phys_pkg_id,
|
||||
|
||||
.get_apic_id = numachip2_get_apic_id,
|
||||
.set_apic_id = numachip2_set_apic_id,
|
||||
.apic_id_mask = 0xffU << 24,
|
||||
|
||||
.cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and,
|
||||
|
||||
.send_IPI_mask = numachip_send_IPI_mask,
|
||||
.send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself,
|
||||
.send_IPI_allbutself = numachip_send_IPI_allbutself,
|
||||
.send_IPI_all = numachip_send_IPI_all,
|
||||
.send_IPI_self = numachip_send_IPI_self,
|
||||
|
||||
.wakeup_secondary_cpu = numachip_wakeup_secondary,
|
||||
.inquire_remote_apic = NULL, /* REMRD not supported */
|
||||
|
||||
.read = native_apic_mem_read,
|
||||
.write = native_apic_mem_write,
|
||||
.eoi_write = native_apic_mem_write,
|
||||
.icr_read = native_apic_icr_read,
|
||||
.icr_write = native_apic_icr_write,
|
||||
.wait_icr_idle = native_apic_wait_icr_idle,
|
||||
.safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
|
||||
};
|
||||
|
||||
apic_driver(apic_numachip2);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user