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ARM: 6184/2: ux500: use neutral PRCMU base

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The MTU wallclock timing fix-up patch was hardwired to the DB8500
causing a regression. This makes it work on the DB5500 as well.

Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Linus Walleij 2010-06-23 07:59:48 +01:00 committed by Russell King
parent 398aa66827
commit d9e38040cc
2 changed files with 2 additions and 1 deletions
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2
arch/arm/mach-ux500/clock.c
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@ -131,7 +131,7 @@ EXPORT_SYMBOL(clk_disable);
*/
static unsigned long clk_mtu_get_rate(struct clk *clk)
{
void __iomem *addr = __io_address(U8500_PRCMU_BASE)
void __iomem *addr = __io_address(UX500_PRCMU_BASE)
+ PRCM_TCR;
u32 tcr = readl(addr);
int mtu = (int) clk->data;

1
arch/arm/mach-ux500/cpu-db5500.c
View File

@ -21,6 +21,7 @@ static struct map_desc u5500_io_desc[] __initdata = {
__IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K),
__IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K),
__IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K),
__IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K),
};
static struct platform_device *u5500_platform_devs[] __initdata = {