From 479f8df04c4b7b1dd53b8c2e5b157b678c8a319c Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 14 May 2015 09:49:14 -0500 Subject: [PATCH 1/5] ARM: socfpga: dts: add the a9-scu node for arria10 Add a dts node for the A9 SCU on the Arria10 platform. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 8a05c47fd57f..4cf0733b930b 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -281,6 +281,11 @@ reg = <0xffd05000 0x100>; }; + scu: snoop-control-unit@ffffc000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xffffc000 0x100>; + }; + sysmgr: sysmgr@ffd06000 { compatible = "altr,sys-mgr", "syscon"; reg = <0xffd06000 0x300>; From ebbce1bbc4f25c0ca68f66df54ea5e8eefa90da5 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 22 May 2015 23:00:10 -0500 Subject: [PATCH 2/5] ARM: socfpga: dts: add enable-method property for cpu nodes Add the enable-method property for the cpu node on socfpga.dtsi and socfpga_arria10.dtsi. This is for CPU_METHOD_OF_DECLARE to use to enable the secondary core. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index d9176e606173..3a02b417ba87 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -36,6 +36,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "altr,socfpga-smp"; cpu@0 { compatible = "arm,cortex-a9"; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 4cf0733b930b..774e041b2572 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -36,6 +36,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "altr,socfpga-a10-smp"; cpu@0 { compatible = "arm,cortex-a9"; From 4c060b89c1af20b3a9d6393072ac85b4a3ccc300 Mon Sep 17 00:00:00 2001 From: Alan Tull Date: Tue, 2 Jun 2015 18:35:39 +0000 Subject: [PATCH 3/5] ARM: socfpga: dts: add sdram controller dt binding doc Add binding doc for Altera SOCFPGA SDRAM controller. Signed-off-by: Alan Tull Signed-off-by: Dinh Nguyen --- .../bindings/arm/altera/socfpga-sdram-controller.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt new file mode 100644 index 000000000000..77ca635765e1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt @@ -0,0 +1,12 @@ +Altera SOCFPGA SDRAM Controller + +Required properties: +- compatible : Should contain "altr,sdr-ctl" and "syscon". + syscon is required by the Altera SOCFPGA SDRAM EDAC. +- reg : Should contain 1 register range (address and length) + +Example: + sdr: sdr@ffc25000 { + compatible = "altr,sdr-ctl", "syscon"; + reg = <0xffc25000 0x1000>; + }; From 81638f1b9f9990b036c63bf20515779a7f41dc6f Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 29 May 2015 14:33:02 +0000 Subject: [PATCH 4/5] ARM: socfpga: socrates: enable gpio0/1 Enable the gpio0+1 controller. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5_socrates.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts index a1814b457450..a81f33deaa3a 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts @@ -36,6 +36,14 @@ status = "okay"; }; +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + &i2c0 { status = "okay"; From e0e6f74801e1d027fa172d47b3e2515027f4728e Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 29 May 2015 14:33:03 +0000 Subject: [PATCH 5/5] ARM: socfpga: socrates: add gpio-leds The SOCrates has three HPS LEDs that can be turned on/off via gpio. Use the first one has heartbeat and add the other two as free LEDs. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- .../boot/dts/socfpga_cyclone5_socrates.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts index a81f33deaa3a..019dd2fea208 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts @@ -30,6 +30,9 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; + + leds: gpio-leds { + }; }; &gmac1 { @@ -53,6 +56,26 @@ }; }; +&leds { + compatible = "gpio-leds"; + + led@0 { + label = "led:green:heartbeat"; + gpios = <&porta 28 1>; + linux,default-trigger = "heartbeat"; + }; + + led@1 { + label = "led:green:D7"; + gpios = <&portb 19 1>; + }; + + led@2 { + label = "led:green:D8"; + gpios = <&portb 25 1>; + }; +}; + &mmc { status = "okay"; };