drm/amdgpu: let mode2 reset fallback to default when failure
- introduce AMDGPU_SKIP_MODE2_RESET flag - let mode2 reset fallback to default reset method if failed v2: move this part out from the asic specific part Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -135,6 +135,7 @@ static void amdgpu_amdkfd_reset_work(struct work_struct *work)
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reset_context.method = AMD_RESET_METHOD_NONE;
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reset_context.reset_req_dev = adev;
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clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
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clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
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amdgpu_device_gpu_recover(adev, NULL, &reset_context);
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}
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@ -5148,6 +5148,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
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reset_context->job = job;
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reset_context->hive = hive;
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/*
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* Build list of devices to reset.
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* In case we are in XGMI hive mode, resort the device list
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@ -5267,8 +5268,11 @@ retry: /* Rest of adevs pre asic reset from XGMI hive. */
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amdgpu_ras_resume(adev);
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} else {
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r = amdgpu_do_asic_reset(device_list_handle, reset_context);
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if (r && r == -EAGAIN)
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if (r && r == -EAGAIN) {
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set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags);
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adev->asic_reset_res = 0;
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goto retry;
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}
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}
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skip_hw_reset:
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@ -5699,6 +5703,7 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
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reset_context.reset_req_dev = adev;
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set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
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set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
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set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
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adev->no_hw_access = true;
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r = amdgpu_device_pre_asic_reset(adev, &reset_context);
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@ -71,6 +71,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
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reset_context.method = AMD_RESET_METHOD_NONE;
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reset_context.reset_req_dev = adev;
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clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
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clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
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r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context);
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if (r)
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@ -1949,6 +1949,7 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)
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reset_context.method = AMD_RESET_METHOD_NONE;
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reset_context.reset_req_dev = adev;
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clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
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clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
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amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
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}
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@ -74,6 +74,9 @@ int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
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{
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struct amdgpu_reset_handler *reset_handler = NULL;
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if (test_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags))
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return -ENOSYS;
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if (adev->reset_cntl && adev->reset_cntl->get_reset_handler)
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reset_handler = adev->reset_cntl->get_reset_handler(
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adev->reset_cntl, reset_context);
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@ -90,6 +93,9 @@ int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
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int ret;
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struct amdgpu_reset_handler *reset_handler = NULL;
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if (test_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags))
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return -ENOSYS;
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if (adev->reset_cntl)
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reset_handler = adev->reset_cntl->get_reset_handler(
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adev->reset_cntl, reset_context);
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@ -30,6 +30,7 @@ enum AMDGPU_RESET_FLAGS {
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AMDGPU_NEED_FULL_RESET = 0,
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AMDGPU_SKIP_HW_RESET = 1,
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AMDGPU_SKIP_MODE2_RESET = 2,
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};
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struct amdgpu_reset_context {
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@ -290,6 +290,7 @@ flr_done:
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reset_context.method = AMD_RESET_METHOD_NONE;
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reset_context.reset_req_dev = adev;
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clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
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clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
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amdgpu_device_gpu_recover(adev, NULL, &reset_context);
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}
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@ -317,6 +317,7 @@ flr_done:
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reset_context.method = AMD_RESET_METHOD_NONE;
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reset_context.reset_req_dev = adev;
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clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
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clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
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amdgpu_device_gpu_recover(adev, NULL, &reset_context);
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}
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@ -529,6 +529,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work)
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reset_context.method = AMD_RESET_METHOD_NONE;
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reset_context.reset_req_dev = adev;
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clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
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clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
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amdgpu_device_gpu_recover(adev, NULL, &reset_context);
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}
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