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drm/msm/dpu: fetch DPU configuration from match data

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In email discussion it was noted that there can be different SoC device
having slightly different SoC features, but sharing the same DPU hw
revision. Stop fetching catalog data using core_rev and use platform's
match data instead.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/530891/
Link: https://lore.kernel.org/r/20230404130622.509628-42-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Dmitry Baryshkov 2023-04-04 16:06:21 +03:00
parent e5edf65453
commit dac76a0144
17 changed files with 46 additions and 83 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
View File

@ -176,7 +176,7 @@ static const struct dpu_perf_cfg msm8998_perf_data = {
.bw_inefficiency_factor = 120,
};
static const struct dpu_mdss_cfg msm8998_dpu_cfg = {
const struct dpu_mdss_cfg dpu_msm8998_cfg = {
.caps = &msm8998_dpu_caps,
.ubwc = &msm8998_ubwc_cfg,
.mdp_count = ARRAY_SIZE(msm8998_mdp),

2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
View File

@ -174,7 +174,7 @@ static const struct dpu_perf_cfg sdm845_perf_data = {
.bw_inefficiency_factor = 120,
};
static const struct dpu_mdss_cfg sdm845_dpu_cfg = {
const struct dpu_mdss_cfg dpu_sdm845_cfg = {
.caps = &sdm845_dpu_caps,
.ubwc = &sdm845_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sdm845_mdp),

2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
View File

@ -197,7 +197,7 @@ static const struct dpu_perf_cfg sm8150_perf_data = {
.bw_inefficiency_factor = 120,
};
static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
const struct dpu_mdss_cfg dpu_sm8150_cfg = {
.caps = &sm8150_dpu_caps,
.ubwc = &sm8150_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sm8150_mdp),

2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
View File

@ -179,7 +179,7 @@ static const struct dpu_perf_cfg sc8180x_perf_data = {
.bw_inefficiency_factor = 120,
};
static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
.caps = &sc8180x_dpu_caps,
.ubwc = &sc8180x_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sc8180x_mdp),

2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
View File

@ -203,7 +203,7 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
.bw_inefficiency_factor = 120,
};
static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
const struct dpu_mdss_cfg dpu_sm8250_cfg = {
.caps = &sm8250_dpu_caps,
.ubwc = &sm8250_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sm8250_mdp),

2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
View File

@ -122,7 +122,7 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
.bw_inefficiency_factor = 120,
};
static const struct dpu_mdss_cfg sc7180_dpu_cfg = {
const struct dpu_mdss_cfg dpu_sc7180_cfg = {
.caps = &sc7180_dpu_caps,
.ubwc = &sc7180_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sc7180_mdp),

2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
View File

@ -99,7 +99,7 @@ static const struct dpu_perf_cfg sm6115_perf_data = {
.bw_inefficiency_factor = 120,
};
static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
const struct dpu_mdss_cfg dpu_sm6115_cfg = {
.caps = &sm6115_dpu_caps,
.ubwc = &sm6115_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sm6115_mdp),

2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
View File

@ -89,7 +89,7 @@ static const struct dpu_perf_cfg qcm2290_perf_data = {
.bw_inefficiency_factor = 120,
};
static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
.caps = &qcm2290_dpu_caps,
.ubwc = &qcm2290_ubwc_cfg,
.mdp_count = ARRAY_SIZE(qcm2290_mdp),

2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
View File

@ -190,7 +190,7 @@ static const struct dpu_perf_cfg sm8350_perf_data = {
.bw_inefficiency_factor = 120,
};
static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
const struct dpu_mdss_cfg dpu_sm8350_cfg = {
.caps = &sm8350_dpu_caps,
.ubwc = &sm8350_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sm8350_mdp),

2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
View File

@ -127,7 +127,7 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
.bw_inefficiency_factor = 120,
};
static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
const struct dpu_mdss_cfg dpu_sc7280_cfg = {
.caps = &sc7280_dpu_caps,
.ubwc = &sc7280_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sc7280_mdp),

2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
View File

@ -181,7 +181,7 @@ static const struct dpu_perf_cfg sc8280xp_perf_data = {
.bw_inefficiency_factor = 120,
};
static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = {
const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
.caps = &sc8280xp_dpu_caps,
.ubwc = &sc8280xp_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sc8280xp_mdp),

2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
View File

@ -198,7 +198,7 @@ static const struct dpu_perf_cfg sm8450_perf_data = {
.bw_inefficiency_factor = 120,
};
static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
const struct dpu_mdss_cfg dpu_sm8450_cfg = {
.caps = &sm8450_dpu_caps,
.ubwc = &sm8450_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sm8450_mdp),

2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
View File

@ -203,7 +203,7 @@ static const struct dpu_perf_cfg sm8550_perf_data = {
.bw_inefficiency_factor = 120,
};
static const struct dpu_mdss_cfg sm8550_dpu_cfg = {
const struct dpu_mdss_cfg dpu_sm8550_cfg = {
.caps = &sm8550_dpu_caps,
.ubwc = &sm8550_ubwc_cfg,
.mdp_count = ARRAY_SIZE(sm8550_mdp),

34
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
View File

@ -803,37 +803,3 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_8_1_sm8450.h"
#include "catalog/dpu_9_0_sm8550.h"
static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
{ .hw_rev = DPU_HW_VER_300, .dpu_cfg = &msm8998_dpu_cfg},
{ .hw_rev = DPU_HW_VER_301, .dpu_cfg = &msm8998_dpu_cfg},
{ .hw_rev = DPU_HW_VER_400, .dpu_cfg = &sdm845_dpu_cfg},
{ .hw_rev = DPU_HW_VER_401, .dpu_cfg = &sdm845_dpu_cfg},
{ .hw_rev = DPU_HW_VER_500, .dpu_cfg = &sm8150_dpu_cfg},
{ .hw_rev = DPU_HW_VER_501, .dpu_cfg = &sm8150_dpu_cfg},
{ .hw_rev = DPU_HW_VER_510, .dpu_cfg = &sc8180x_dpu_cfg},
{ .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
{ .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
{ .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg},
{ .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
{ .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
{ .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
{ .hw_rev = DPU_HW_VER_800, .dpu_cfg = &sc8280xp_dpu_cfg},
{ .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg},
{ .hw_rev = DPU_HW_VER_900, .dpu_cfg = &sm8550_dpu_cfg},
};
const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev)
{
int i;
for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) {
if (cfg_handler[i].hw_rev == hw_rev)
return cfg_handler[i].dpu_cfg;
}
DPU_ERROR("unsupported chipset id:%X\n", hw_rev);
return ERR_PTR(-ENODEV);
}

26
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
View File

@ -910,18 +910,18 @@ struct dpu_mdss_cfg {
unsigned long mdss_irqs;
};
struct dpu_mdss_hw_cfg_handler {
u32 hw_rev;
const struct dpu_mdss_cfg *dpu_cfg;
};
/**
* dpu_hw_catalog_init - dpu hardware catalog init API retrieves
* hardcoded target specific catalog information in config structure
* @hw_rev: caller needs provide the hardware revision.
*
* Return: dpu config structure
*/
const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev);
extern const struct dpu_mdss_cfg dpu_msm8998_cfg;
extern const struct dpu_mdss_cfg dpu_sdm845_cfg;
extern const struct dpu_mdss_cfg dpu_sm8150_cfg;
extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
extern const struct dpu_mdss_cfg dpu_sm8450_cfg;
extern const struct dpu_mdss_cfg dpu_sm8550_cfg;
#endif /* _DPU_HW_CATALOG_H */

42
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
View File

@ -995,6 +995,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
struct dpu_kms *dpu_kms;
struct drm_device *dev;
int i, rc = -EINVAL;
u32 core_rev;
if (!kms) {
DPU_ERROR("invalid kms\n");
@ -1044,17 +1045,14 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
if (rc < 0)
goto error;
dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0);
core_rev = readl_relaxed(dpu_kms->mmio + 0x0);
pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev);
pr_info("dpu hardware revision:0x%x\n", core_rev);
dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev);
if (IS_ERR_OR_NULL(dpu_kms->catalog)) {
rc = PTR_ERR(dpu_kms->catalog);
if (!dpu_kms->catalog)
rc = -EINVAL;
DPU_ERROR("catalog init failed: %d\n", rc);
dpu_kms->catalog = NULL;
dpu_kms->catalog = of_device_get_match_data(dev->dev);
if (!dpu_kms->catalog) {
DPU_ERROR("device config not known!\n");
rc = -EINVAL;
goto power_error;
}
@ -1280,19 +1278,19 @@ static const struct dev_pm_ops dpu_pm_ops = {
};
static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,msm8998-dpu", },
{ .compatible = "qcom,qcm2290-dpu", },
{ .compatible = "qcom,sdm845-dpu", },
{ .compatible = "qcom,sc7180-dpu", },
{ .compatible = "qcom,sc7280-dpu", },
{ .compatible = "qcom,sc8180x-dpu", },
{ .compatible = "qcom,sc8280xp-dpu", },
{ .compatible = "qcom,sm6115-dpu", },
{ .compatible = "qcom,sm8150-dpu", },
{ .compatible = "qcom,sm8250-dpu", },
{ .compatible = "qcom,sm8350-dpu", },
{ .compatible = "qcom,sm8450-dpu", },
{ .compatible = "qcom,sm8550-dpu", },
{ .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, },
{ .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, },
{ .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, },
{ .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, },
{ .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, },
{ .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
{ .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
{ .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
{ .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
{ .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
{}
};
MODULE_DEVICE_TABLE(of, dpu_dt_match);

1
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
View File

@ -68,7 +68,6 @@
struct dpu_kms {
struct msm_kms base;
struct drm_device *dev;
int core_rev;
const struct dpu_mdss_cfg *catalog;
/* io/register spaces: */