diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt b/Documentation/devicetree/bindings/net/mediatek-dwmac.txt index 4de479b4d44d..8a08621a5b54 100644 --- a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt +++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.txt @@ -22,33 +22,25 @@ Required properties: Optional properties: - mediatek,tx-delay-ps: TX clock delay macro value. Default is 0. - It should be defined for rgmii/rgmii-rxid/mii interface. + It should be defined for RGMII/MII interface. - mediatek,rx-delay-ps: RX clock delay macro value. Default is 0. - It should be defined for rgmii/rgmii-txid/mii/rmii interface. -Both delay properties need to be a multiple of 170 for fine-tune rgmii, -range 0~31*170. -Both delay properties need to be a multiple of 550 for coarse-tune rgmii, -range 0~31*550. -Both delay properties need to be a multiple of 550 for mii/rmii, -range 0~31*550. + It should be defined for RGMII/MII/RMII interface. +Both delay properties need to be a multiple of 170 for RGMII interface, +or will round down. Range 0~31*170. +Both delay properties need to be a multiple of 550 for MII/RMII interface, +or will round down. Range 0~31*550. -- mediatek,fine-tune: boolean property, if present indicates that fine delay - is selected for rgmii interface. - If present, tx-delay-ps/rx-delay-ps is 170+/-50ps per stage. - Else tx-delay-ps/rx-delay-ps of coarse delay macro is 0.55+/-0.2ns per stage. - This property do not apply to non-rgmii PHYs. - Only coarse-tune delay is supported for mii/rmii PHYs. -- mediatek,rmii-rxc: boolean property, if present indicates that the rmii +- mediatek,rmii-rxc: boolean property, if present indicates that the RMII reference clock, which is from external PHYs, is connected to RXC pin on MT2712 SoC. Otherwise, is connected to TXC pin. - mediatek,txc-inverse: boolean property, if present indicates that - 1. tx clock will be inversed in mii/rgmii case, + 1. tx clock will be inversed in MII/RGMII case, 2. tx clock inside MAC will be inversed relative to reference clock - which is from external PHYs in rmii case, and it rarely happen. + which is from external PHYs in RMII case, and it rarely happen. - mediatek,rxc-inverse: boolean property, if present indicates that - 1. rx clock will be inversed in mii/rgmii case. - 2. reference clock will be inversed when arrived at MAC in rmii case. + 1. rx clock will be inversed in MII/RGMII case. + 2. reference clock will be inversed when arrived at MAC in RMII case. - assigned-clocks: mac_main and ptp_ref clocks - assigned-clock-parents: parent clocks of the assigned clocks @@ -76,7 +68,6 @@ Example: mediatek,pericfg = <&pericfg>; mediatek,tx-delay-ps = <1530>; mediatek,rx-delay-ps = <1530>; - mediatek,fine-tune; mediatek,rmii-rxc; mediatek,txc-inverse; mediatek,rxc-inverse; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c index e400cbdc3419..bf2562995fc8 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -44,7 +44,6 @@ struct mac_delay_struct { u32 rx_delay; bool tx_inv; bool rx_inv; - bool fine_tune; }; struct mediatek_dwmac_plat_data { @@ -105,16 +104,28 @@ static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat) return 0; } -static void mt2712_delay_ps2stage(struct mac_delay_struct *mac_delay) +static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat) { - if (mac_delay->fine_tune) { - /* 170ps per stage for fine tune delay macro circuit*/ - mac_delay->tx_delay /= 170; - mac_delay->rx_delay /= 170; - } else { - /* 550ps per stage for coarse tune delay macro circuit*/ + struct mac_delay_struct *mac_delay = &plat->mac_delay; + + switch (plat->phy_mode) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RMII: + /* 550ps per stage for MII/RMII */ mac_delay->tx_delay /= 550; mac_delay->rx_delay /= 550; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + /* 170ps per stage for RGMII */ + mac_delay->tx_delay /= 170; + mac_delay->rx_delay /= 170; + break; + default: + dev_err(plat->dev, "phy interface not supported\n"); + break; } } @@ -123,7 +134,7 @@ static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat) struct mac_delay_struct *mac_delay = &plat->mac_delay; u32 delay_val = 0, fine_val = 0; - mt2712_delay_ps2stage(mac_delay); + mt2712_delay_ps2stage(plat); switch (plat->phy_mode) { case PHY_INTERFACE_MODE_MII: @@ -167,51 +178,18 @@ static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat) fine_val = ETH_RMII_DLY_TX_INV; break; case PHY_INTERFACE_MODE_RGMII: - /* the PHY is not responsible for inserting any internal - * delay by itself in PHY_INTERFACE_MODE_RGMII case, - * so Ethernet MAC will insert delays for both transmit - * and receive path here. - */ - if (mac_delay->fine_tune) - fine_val = ETH_FINE_DLY_GTXC | ETH_FINE_DLY_RXC; - - delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); - delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay); - delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv); - - delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); - delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); - delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); - break; case PHY_INTERFACE_MODE_RGMII_TXID: - /* the PHY should insert an internal delay for the transmit - * path in PHY_INTERFACE_MODE_RGMII_TXID case, - * so Ethernet MAC will insert the delay for receive path here. - */ - if (mac_delay->fine_tune) - fine_val = ETH_FINE_DLY_RXC; - - delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); - delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); - delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); - break; case PHY_INTERFACE_MODE_RGMII_RXID: - /* the PHY should insert an internal delay for the receive - * path in PHY_INTERFACE_MODE_RGMII_RXID case, - * so Ethernet MAC will insert the delay for transmit path here. - */ - if (mac_delay->fine_tune) - fine_val = ETH_FINE_DLY_GTXC; + case PHY_INTERFACE_MODE_RGMII_ID: + fine_val = ETH_FINE_DLY_GTXC | ETH_FINE_DLY_RXC; delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay); delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv); - break; - case PHY_INTERFACE_MODE_RGMII_ID: - /* the PHY should insert internal delays for both transmit - * and receive path in PHY_INTERFACE_MODE_RGMII_RXID case, - * so Ethernet MAC will NOT insert any delay here. - */ + + delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); + delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); + delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); break; default: dev_err(plat->dev, "phy interface not supported\n"); @@ -270,7 +248,6 @@ static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat) mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse"); mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse"); - mac_delay->fine_tune = of_property_read_bool(plat->np, "mediatek,fine-tune"); plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc"); return 0;