iio: at91: fix adc_clk overflow
The adc_clk variable is currently defined using a 32-bits unsigned integer, which will overflow under some very valid range of operations. Such overflow will occur if, for example, the parent clock is set to a 20MHz frequency and the ADC startup time is larger than 215ns. To fix this, introduce an intermediate variable holding the clock rate in kHz. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
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@ -556,7 +556,7 @@ static const struct iio_info at91_adc_info = {
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static int at91_adc_probe(struct platform_device *pdev)
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{
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unsigned int prsc, mstrclk, ticks, adc_clk, shtim;
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unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
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int ret;
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struct iio_dev *idev;
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struct at91_adc_state *st;
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@ -649,6 +649,7 @@ static int at91_adc_probe(struct platform_device *pdev)
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*/
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mstrclk = clk_get_rate(st->clk);
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adc_clk = clk_get_rate(st->adc_clk);
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adc_clk_khz = adc_clk / 1000;
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prsc = (mstrclk / (2 * adc_clk)) - 1;
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if (!st->startup_time) {
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@ -662,15 +663,15 @@ static int at91_adc_probe(struct platform_device *pdev)
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* defined in the electrical characteristics of the board, divided by 8.
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* The formula thus is : Startup Time = (ticks + 1) * 8 / ADC Clock
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*/
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ticks = round_up((st->startup_time * adc_clk /
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1000000) - 1, 8) / 8;
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ticks = round_up((st->startup_time * adc_clk_khz /
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1000) - 1, 8) / 8;
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/*
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* a minimal Sample and Hold Time is necessary for the ADC to guarantee
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* the best converted final value between two channels selection
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* The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
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*/
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shtim = round_up((st->sample_hold_time * adc_clk /
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1000000) - 1, 1);
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shtim = round_up((st->sample_hold_time * adc_clk_khz /
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1000) - 1, 1);
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reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
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reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
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