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iio: at91: fix adc_clk overflow

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The adc_clk variable is currently defined using a 32-bits unsigned integer,
which will overflow under some very valid range of operations.

Such overflow will occur if, for example, the parent clock is set to a
20MHz frequency and the ADC startup time is larger than 215ns.

To fix this, introduce an intermediate variable holding the clock rate
in kHz.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This commit is contained in:
Josh Wu 2013-08-27 12:28:00 +01:00 committed by Jonathan Cameron
parent c3cb718acc
commit db10e20117
1 changed files with 6 additions and 5 deletions
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11
drivers/iio/adc/at91_adc.c
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@ -556,7 +556,7 @@ static const struct iio_info at91_adc_info = {
static int at91_adc_probe(struct platform_device *pdev) static int at91_adc_probe(struct platform_device *pdev)
{ {
unsigned int prsc, mstrclk, ticks, adc_clk, shtim; unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
int ret; int ret;
struct iio_dev *idev; struct iio_dev *idev;
struct at91_adc_state *st; struct at91_adc_state *st;
@ -649,6 +649,7 @@ static int at91_adc_probe(struct platform_device *pdev)
*/ */
mstrclk = clk_get_rate(st->clk); mstrclk = clk_get_rate(st->clk);
adc_clk = clk_get_rate(st->adc_clk); adc_clk = clk_get_rate(st->adc_clk);
adc_clk_khz = adc_clk / 1000;
prsc = (mstrclk / (2 * adc_clk)) - 1; prsc = (mstrclk / (2 * adc_clk)) - 1;
if (!st->startup_time) { if (!st->startup_time) {
@ -662,15 +663,15 @@ static int at91_adc_probe(struct platform_device *pdev)
* defined in the electrical characteristics of the board, divided by 8. * defined in the electrical characteristics of the board, divided by 8.
* The formula thus is : Startup Time = (ticks + 1) * 8 / ADC Clock * The formula thus is : Startup Time = (ticks + 1) * 8 / ADC Clock
*/ */
ticks = round_up((st->startup_time * adc_clk / ticks = round_up((st->startup_time * adc_clk_khz /
1000000) - 1, 8) / 8; 1000) - 1, 8) / 8;
/* /*
* a minimal Sample and Hold Time is necessary for the ADC to guarantee * a minimal Sample and Hold Time is necessary for the ADC to guarantee
* the best converted final value between two channels selection * the best converted final value between two channels selection
* The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
*/ */
shtim = round_up((st->sample_hold_time * adc_clk / shtim = round_up((st->sample_hold_time * adc_clk_khz /
1000000) - 1, 1); 1000) - 1, 1);
reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask; reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask; reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;