diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/arm/xilinx.yaml index f52c7e8ce654..a0b1ae6e3e71 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.yaml +++ b/Documentation/devicetree/bindings/arm/xilinx.yaml @@ -87,6 +87,7 @@ properties: - xlnx,zynqmp-zcu102-revA - xlnx,zynqmp-zcu102-revB - xlnx,zynqmp-zcu102-rev1.0 + - xlnx,zynqmp-zcu102-rev1.1 - const: xlnx,zynqmp-zcu102 - const: xlnx,zynqmp diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index 11fb4fd3ebd4..083ed52337fd 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.1.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index cf5295224750..1e0b1bca7c94 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -2,7 +2,7 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -40,6 +40,17 @@ }; }; +&zynqmp_firmware { + zynqmp_clk: clock-controller { + #clock-cells = <1>; + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, + <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", + "aux_ref_clk", "gt_crx_ref_clk"; + }; +}; + &can0 { clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts index 2e05fa416955..f1598527e5ec 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -19,6 +19,7 @@ aliases { serial0 = &uart0; serial1 = &dcc; + spi0 = &qspi; }; chosen { @@ -36,6 +37,19 @@ status = "okay"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &sata { status = "okay"; /* SATA OOB timing settings */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts index 3d0aaa02f184..04efa1683eaa 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2019, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek * Siva Durga Prasad Paladugu @@ -20,6 +20,7 @@ aliases { serial0 = &uart0; serial1 = &dcc; + spi0 = &qspi; }; chosen { @@ -37,6 +38,19 @@ status = "okay"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts index 66a90483b004..e971ba8c1418 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek * Siva Durga Prasad Paladugu @@ -20,6 +20,7 @@ aliases { serial0 = &uart0; serial1 = &dcc; + spi0 = &qspi; }; chosen { @@ -37,6 +38,21 @@ status = "okay"; }; +&gpio { + status = "okay"; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index 69f6e4610739..b05be2552826 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2019, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -11,7 +11,9 @@ #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" +#include #include +#include / { model = "ZynqMP zc1751-xm015-dc1 RevA"; @@ -24,6 +26,8 @@ mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; + spi0 = &qspi; + usb0 = &usb0; }; chosen { @@ -35,6 +39,24 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + + clock_si5338_0: clk27 { /* u55 SI5338-GM */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clock_si5338_2: clk26 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clock_si5338_3: clk150 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <150000000>; + }; }; &fpd_dma_chan1 { @@ -73,6 +95,8 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@0 { reg = <0>; }; @@ -80,12 +104,19 @@ &gpio { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { status = "okay"; clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ @@ -93,6 +124,236 @@ }; }; +&pinctrl0 { + status = "okay"; + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_9_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_9_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_36_grp", "gpio0_37_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_36_grp", "gpio0_37_grp"; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_uart0_default: uart0-default { + mux { + groups = "uart0_8_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_8_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO34"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO35"; + bias-disable; + }; + }; + + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + }; + + pinctrl_gem3_default: gem3-default { + mux { + function = "ethernet3"; + groups = "ethernet3_0_grp"; + }; + + conf { + groups = "ethernet3_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", + "MIO75"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", + "MIO69"; + bias-disable; + low-power-enable; + }; + + mux-mdio { + function = "mdio3"; + groups = "mdio3_0_grp"; + }; + + conf-mdio { + groups = "mdio3_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + }; + + pinctrl_sdhci0_default: sdhci0-default { + mux { + groups = "sdio0_0_grp"; + function = "sdio0"; + }; + + conf { + groups = "sdio0_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux-cd { + groups = "sdio0_cd_0_grp"; + function = "sdio0_cd"; + }; + + conf-cd { + groups = "sdio0_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux-wp { + groups = "sdio0_wp_0_grp"; + function = "sdio0_wp"; + }; + + conf-wp { + groups = "sdio0_wp_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_sdhci1_default: sdhci1-default { + mux { + groups = "sdio1_0_grp"; + function = "sdio1"; + }; + + conf { + groups = "sdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux-cd { + groups = "sdio1_cd_0_grp"; + function = "sdio1_cd"; + }; + + conf-cd { + groups = "sdio1_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux-wp { + groups = "sdio1_wp_0_grp"; + function = "sdio1_wp"; + }; + + conf-wp { + groups = "sdio1_wp_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_gpio_default: gpio-default { + mux { + function = "gpio0"; + groups = "gpio0_38_grp"; + }; + + conf { + groups = "gpio0_38_grp"; + bias-disable; + slew-rate = ; + power-source = ; + }; + }; +}; + +&psgtr { + status = "okay"; + /* dp, usb3, sata */ + clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; + clock-names = "ref1", "ref2", "ref3"; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; @@ -108,25 +369,60 @@ ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* eMMC */ &sdhci0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; + xlnx,mio-bank = <0>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; + /* + * This property should be removed for supporting UHS mode + */ + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1_default>; + xlnx,mio-bank = <1>; }; &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; - dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; +}; + +&zynqmp_dpdma { + status = "okay"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 0>, + <&psgtr 0 PHY_TYPE_DP 1 1>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index 4a86efa32d68..938b76bd0527 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2019, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -12,14 +12,13 @@ #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" #include +#include / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { - can0 = &can0; - can1 = &can1; ethernet0 = &gem2; i2c0 = &i2c0; rtc0 = &rtc; @@ -27,6 +26,7 @@ serial1 = &uart1; spi0 = &spi0; spi1 = &spi1; + usb0 = &usb1; }; chosen { @@ -42,10 +42,14 @@ &can0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; }; &fpd_dma_chan1 { @@ -84,6 +88,8 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem2_default>; phy0: ethernet-phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; @@ -100,6 +106,11 @@ &i2c0 { status = "okay"; clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; @@ -115,6 +126,311 @@ }; }; +&nand0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand0_default>; + arasan,has-mdma; + + nand@0 { + reg = <0x0>; + #address-cells = <0x2>; + #size-cells = <0x1>; + nand-ecc-mode = "soft"; + nand-ecc-algo = "bch"; + nand-rb = <0>; + label = "main-storage-0"; + }; + nand@1 { + reg = <0x1>; + #address-cells = <0x2>; + #size-cells = <0x1>; + nand-ecc-mode = "soft"; + nand-ecc-algo = "bch"; + nand-rb = <0>; + label = "main-storage-1"; + }; +}; + +&pinctrl0 { + status = "okay"; + pinctrl_can0_default: can0-default { + mux { + function = "can0"; + groups = "can0_9_grp"; + }; + + conf { + groups = "can0_9_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO38"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO39"; + bias-disable; + }; + }; + + pinctrl_can1_default: can1-default { + mux { + function = "can1"; + groups = "can1_8_grp"; + }; + + conf { + groups = "can1_8_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO33"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO32"; + bias-disable; + }; + }; + + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_1_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_1_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_6_grp", "gpio0_7_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_6_grp", "gpio0_7_grp"; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_uart0_default: uart0-default { + mux { + groups = "uart0_10_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_10_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO42"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO43"; + bias-disable; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_10_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_10_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO41"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO40"; + bias-disable; + }; + }; + + pinctrl_usb1_default: usb1-default { + mux { + groups = "usb1_0_grp"; + function = "usb1"; + }; + + conf { + groups = "usb1_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + }; + }; + + pinctrl_gem2_default: gem2-default { + mux { + function = "ethernet2"; + groups = "ethernet2_0_grp"; + }; + + conf { + groups = "ethernet2_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", + "MIO63"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", + "MIO57"; + bias-disable; + low-power-enable; + }; + + mux-mdio { + function = "mdio2"; + groups = "mdio2_0_grp"; + }; + + conf-mdio { + groups = "mdio2_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + }; + + pinctrl_nand0_default: nand0-default { + mux { + groups = "nand0_0_grp"; + function = "nand0"; + }; + + conf { + groups = "nand0_0_grp"; + bias-pull-up; + }; + + mux-ce { + groups = "nand0_ce_0_grp"; + function = "nand0_ce"; + }; + + conf-ce { + groups = "nand0_ce_0_grp"; + bias-pull-up; + }; + + mux-rb { + groups = "nand0_rb_0_grp"; + function = "nand0_rb"; + }; + + conf-rb { + groups = "nand0_rb_0_grp"; + bias-pull-up; + }; + + mux-dqs { + groups = "nand0_dqs_0_grp"; + function = "nand0_dqs"; + }; + + conf-dqs { + groups = "nand0_dqs_0_grp"; + bias-pull-up; + }; + }; + + pinctrl_spi0_default: spi0-default { + mux { + groups = "spi0_0_grp"; + function = "spi0"; + }; + + conf { + groups = "spi0_0_grp"; + bias-disable; + slew-rate = ; + power-source = ; + }; + + mux-cs { + groups = "spi0_ss_0_grp", "spi0_ss_1_grp", + "spi0_ss_2_grp"; + function = "spi0_ss"; + }; + + conf-cs { + groups = "spi0_ss_0_grp", "spi0_ss_1_grp", + "spi0_ss_2_grp"; + bias-disable; + }; + }; + + pinctrl_spi1_default: spi1-default { + mux { + groups = "spi1_3_grp"; + function = "spi1"; + }; + + conf { + groups = "spi1_3_grp"; + bias-disable; + slew-rate = ; + power-source = ; + }; + + mux-cs { + groups = "spi1_ss_9_grp", "spi1_ss_10_grp", + "spi1_ss_11_grp"; + function = "spi1_ss"; + }; + + conf-cs { + groups = "spi1_ss_9_grp", "spi1_ss_10_grp", + "spi1_ss_11_grp"; + bias-disable; + }; + }; +}; + &rtc { status = "okay"; }; @@ -122,6 +438,8 @@ &spi0 { status = "okay"; num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { #address-cells = <1>; @@ -131,7 +449,7 @@ reg = <0>; partition@0 { - label = "data"; + label = "spi0-data"; reg = <0x0 0x100000>; }; }; @@ -140,6 +458,8 @@ &spi1 { status = "okay"; num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { #address-cells = <1>; @@ -149,7 +469,7 @@ reg = <0>; partition@0 { - label = "data"; + label = "spi1-data"; reg = <0x0 0x84000>; }; }; @@ -157,14 +477,26 @@ /* ULPI SMSC USB3320 */ &usb1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_default>; +}; + +&dwc3_1 { status = "okay"; dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; }; &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts index 4ea6ef5a7f2b..381cc682cef9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2019, Xilinx, Inc. + * (C) Copyright 2016 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -11,6 +11,7 @@ #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" +#include / { model = "ZynqMP zc1751-xm017-dc3 RevA"; @@ -24,6 +25,8 @@ rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; + usb0 = &usb0; + usb1 = &usb1; }; chosen { @@ -35,6 +38,18 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + + clock_si5338_2: clk26 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clock_si5338_3: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; }; &fpd_dma_chan1 { @@ -107,6 +122,20 @@ clock-frequency = <400000>; }; +/* MT29F64G08AECDBJ4-6 */ +&nand0 { + status = "okay"; + arasan,has-mdma; + num-cs = <2>; +}; + +&psgtr { + status = "okay"; + /* usb3, sata */ + clocks = <&clock_si5338_2>, <&clock_si5338_3>; + clock-names = "ref2", "ref3"; +}; + &rtc { status = "okay"; }; @@ -122,6 +151,8 @@ ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&psgtr 2 PHY_TYPE_SATA 0 3>; }; &sdhci1 { /* emmc with some settings */ @@ -139,12 +170,28 @@ }; &usb0 { + status = "okay"; + phy-names = "usb3-phy"; + phys = <&psgtr 0 PHY_TYPE_USB3 0 2>; +}; + +&dwc3_0 { status = "okay"; dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; - dr_mode = "host"; + phy-names = "usb3-phy"; + phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; +}; + +&dwc3_1 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 2366cd9f091a..05a2b79738af 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2019, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -26,6 +26,7 @@ rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; + spi0 = &qspi; }; chosen { @@ -161,6 +162,19 @@ status = "okay"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; @@ -176,3 +190,11 @@ &watchdog0 { status = "okay"; }; + +&zynqmp_dpdma { + status = "okay"; +}; + +&zynqmp_dpsub { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts index 41934e3525c6..ae2d03d98322 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2019, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Siva Durga Prasad * Michal Simek @@ -13,6 +13,7 @@ #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" #include +#include / { model = "ZynqMP zc1751-xm019-dc5 RevA"; @@ -74,6 +75,8 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem1_default>; phy0: ethernet-phy@0 { reg = <0>; }; @@ -85,41 +88,366 @@ &i2c0 { status = "okay"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>; }; &i2c1 { status = "okay"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>; + +}; + +&pinctrl0 { + status = "okay"; + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_18_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_18_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_74_grp", "gpio0_75_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_74_grp", "gpio0_75_grp"; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_19_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_19_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_76_grp", "gpio0_77_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_76_grp", "gpio0_77_grp"; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_uart0_default: uart0-default { + mux { + groups = "uart0_17_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_17_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO70"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO71"; + bias-disable; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_18_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_18_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO73"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO72"; + bias-disable; + }; + }; + + pinctrl_gem1_default: gem1-default { + mux { + function = "ethernet1"; + groups = "ethernet1_0_grp"; + }; + + conf { + groups = "ethernet1_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48", + "MIO49"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42", + "MIO43"; + bias-disable; + low-power-enable; + }; + + mux-mdio { + function = "mdio1"; + groups = "mdio1_0_grp"; + }; + + conf-mdio { + groups = "mdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + }; + + pinctrl_sdhci0_default: sdhci0-default { + mux { + groups = "sdio0_0_grp"; + function = "sdio0"; + }; + + conf { + groups = "sdio0_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux-cd { + groups = "sdio0_cd_0_grp"; + function = "sdio0_cd"; + }; + + conf-cd { + groups = "sdio0_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux-wp { + groups = "sdio0_wp_0_grp"; + function = "sdio0_wp"; + }; + + conf-wp { + groups = "sdio0_wp_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_watchdog0_default: watchdog0-default { + mux-clk { + groups = "swdt0_clk_1_grp"; + function = "swdt0_clk"; + }; + + conf-clk { + groups = "swdt0_clk_1_grp"; + bias-pull-up; + }; + + mux-rst { + groups = "swdt0_rst_1_grp"; + function = "swdt0_rst"; + }; + + conf-rst { + groups = "swdt0_rst_1_grp"; + bias-disable; + slew-rate = ; + }; + }; + + pinctrl_ttc0_default: ttc0-default { + mux-clk { + groups = "ttc0_clk_0_grp"; + function = "ttc0_clk"; + }; + + conf-clk { + groups = "ttc0_clk_0_grp"; + bias-pull-up; + }; + + mux-wav { + groups = "ttc0_wav_0_grp"; + function = "ttc0_wav"; + }; + + conf-wav { + groups = "ttc0_wav_0_grp"; + bias-disable; + slew-rate = ; + }; + }; + + pinctrl_ttc1_default: ttc1-default { + mux-clk { + groups = "ttc1_clk_0_grp"; + function = "ttc1_clk"; + }; + + conf-clk { + groups = "ttc1_clk_0_grp"; + bias-pull-up; + }; + + mux-wav { + groups = "ttc1_wav_0_grp"; + function = "ttc1_wav"; + }; + + conf-wav { + groups = "ttc1_wav_0_grp"; + bias-disable; + slew-rate = ; + }; + }; + + pinctrl_ttc2_default: ttc2-default { + mux-clk { + groups = "ttc2_clk_0_grp"; + function = "ttc2_clk"; + }; + + conf-clk { + groups = "ttc2_clk_0_grp"; + bias-pull-up; + }; + + mux-wav { + groups = "ttc2_wav_0_grp"; + function = "ttc2_wav"; + }; + + conf-wav { + groups = "ttc2_wav_0_grp"; + bias-disable; + slew-rate = ; + }; + }; + + pinctrl_ttc3_default: ttc3-default { + mux-clk { + groups = "ttc3_clk_0_grp"; + function = "ttc3_clk"; + }; + + conf-clk { + groups = "ttc3_clk_0_grp"; + bias-pull-up; + }; + + mux-wav { + groups = "ttc3_wav_0_grp"; + function = "ttc3_wav"; + }; + + conf-wav { + groups = "ttc3_wav_0_grp"; + bias-disable; + slew-rate = ; + }; + }; }; &sdhci0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; no-1-8-v; + xlnx,mio-bank = <0>; }; &ttc0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ttc0_default>; }; &ttc1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ttc1_default>; }; &ttc2 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ttc2_default>; }; &ttc3 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ttc3_default>; }; &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; }; &watchdog0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_watchdog0_default>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index a53598c3624b..f6aad4159ccd 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2019, Xilinx, Inc. + * (C) Copyright 2016 - 2021, Xilinx, Inc. * * Michal Simek * Nathalie Chan King Choy @@ -15,6 +15,7 @@ #include #include #include +#include #include / { @@ -29,6 +30,8 @@ serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; + usb0 = &usb0; + usb1 = &usb1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; @@ -110,13 +113,13 @@ io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; - si5335a_0: clk26 { + si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; - si5335a_1: clk27 { + si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; @@ -160,6 +163,11 @@ &i2c1 { status = "okay"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; @@ -237,10 +245,225 @@ }; }; +&pinctrl0 { + status = "okay"; + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_1_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_1_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_4_grp", "gpio0_5_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_4_grp", "gpio0_5_grp"; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_sdhci0_default: sdhci0-default { + mux { + groups = "sdio0_3_grp"; + function = "sdio0"; + }; + + conf { + groups = "sdio0_3_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux-cd { + groups = "sdio0_cd_0_grp"; + function = "sdio0_cd"; + }; + + conf-cd { + groups = "sdio0_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_sdhci1_default: sdhci1-default { + mux { + groups = "sdio1_2_grp"; + function = "sdio1"; + }; + + conf { + groups = "sdio1_2_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + }; + + pinctrl_spi0_default: spi0-default { + mux { + groups = "spi0_3_grp"; + function = "spi0"; + }; + + conf { + groups = "spi0_3_grp"; + bias-disable; + slew-rate = ; + power-source = ; + }; + + mux-cs { + groups = "spi0_ss_9_grp"; + function = "spi0_ss"; + }; + + conf-cs { + groups = "spi0_ss_9_grp"; + bias-disable; + }; + + }; + + pinctrl_spi1_default: spi1-default { + mux { + groups = "spi1_0_grp"; + function = "spi1"; + }; + + conf { + groups = "spi1_0_grp"; + bias-disable; + slew-rate = ; + power-source = ; + }; + + mux-cs { + groups = "spi1_ss_0_grp"; + function = "spi1_ss"; + }; + + conf-cs { + groups = "spi1_ss_0_grp"; + bias-disable; + }; + + }; + + pinctrl_uart0_default: uart0-default { + mux { + groups = "uart0_0_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO3"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO2"; + bias-disable; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_0_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO1"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO0"; + bias-disable; + }; + }; + + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + }; + + pinctrl_usb1_default: usb1-default { + mux { + groups = "usb1_0_grp"; + function = "usb1"; + }; + + conf { + groups = "usb1_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + }; + }; +}; + &psgtr { status = "okay"; - /* usb3, dps */ - clocks = <&si5335a_0>, <&si5335a_1>; + /* usb3, dp */ + clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; @@ -253,12 +476,16 @@ status = "okay"; no-1-8-v; disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; xlnx,mio-bank = <0>; }; &sdhci1 { status = "okay"; bus-width = <0x4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio-bank = <0>; non-removable; disable-wp; @@ -279,16 +506,22 @@ status = "okay"; label = "LS-SPI0"; num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0_default>; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; }; &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; @@ -297,19 +530,38 @@ &uart1 { status = "okay"; - + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; +}; + +&dwc3_0 { status = "okay"; dr_mode = "peripheral"; + maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; +}; + +&dwc3_1 { status = "okay"; dr_mode = "host"; + maximum-speed = "super-speed"; }; &watchdog0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts new file mode 100644 index 000000000000..b6798394fcf4 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU102 Rev1.1 + * + * (C) Copyright 2016 - 2020, Xilinx, Inc. + * + * Michal Simek + */ + +#include "zynqmp-zcu102-rev1.0.dts" + +/ { + model = "ZynqMP ZCU102 Rev1.1"; + compatible = "xlnx,zynqmp-zcu102-rev1.1", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index eca6c2de84a7..7b9a88b125d1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2019, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -13,6 +13,7 @@ #include "zynqmp-clk-ccf.dtsi" #include #include +#include #include / { @@ -24,10 +25,13 @@ i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; + spi0 = &qspi; + usb0 = &usb0; }; chosen { @@ -150,6 +154,8 @@ &can1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; }; &dcc { @@ -192,22 +198,32 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; + /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; &gpio { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { status = "okay"; clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; @@ -451,7 +467,6 @@ status = "disabled"; /* unreachable */ reg = <0x20>; }; - max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; @@ -468,6 +483,11 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ @@ -642,6 +662,269 @@ }; }; +&pinctrl0 { + status = "okay"; + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_3_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_3_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_14_grp", "gpio0_15_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_14_grp", "gpio0_15_grp"; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_4_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_4_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_16_grp", "gpio0_17_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_16_grp", "gpio0_17_grp"; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_uart0_default: uart0-default { + mux { + groups = "uart0_4_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_4_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO18"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO19"; + bias-disable; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_5_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_5_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO21"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO20"; + bias-disable; + }; + }; + + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + }; + + pinctrl_gem3_default: gem3-default { + mux { + function = "ethernet3"; + groups = "ethernet3_0_grp"; + }; + + conf { + groups = "ethernet3_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", + "MIO75"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", + "MIO69"; + bias-disable; + low-power-enable; + }; + + mux-mdio { + function = "mdio3"; + groups = "mdio3_0_grp"; + }; + + conf-mdio { + groups = "mdio3_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + }; + + pinctrl_can1_default: can1-default { + mux { + function = "can1"; + groups = "can1_6_grp"; + }; + + conf { + groups = "can1_6_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO25"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO24"; + bias-disable; + }; + }; + + pinctrl_sdhci1_default: sdhci1-default { + mux { + groups = "sdio1_0_grp"; + function = "sdio1"; + }; + + conf { + groups = "sdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux-cd { + groups = "sdio1_cd_0_grp"; + function = "sdio1_cd"; + }; + + conf-cd { + groups = "sdio1_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux-wp { + groups = "sdio1_wp_0_grp"; + function = "sdio1_wp"; + }; + + conf-wp { + groups = "sdio1_wp_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_gpio_default: gpio-default { + mux-sw { + function = "gpio0"; + groups = "gpio0_22_grp", "gpio0_23_grp"; + }; + + conf-sw { + groups = "gpio0_22_grp", "gpio0_23_grp"; + slew-rate = ; + power-source = ; + }; + + mux-msp { + function = "gpio0"; + groups = "gpio0_13_grp", "gpio0_38_grp"; + }; + + conf-msp { + groups = "gpio0_13_grp", "gpio0_38_grp"; + slew-rate = ; + power-source = ; + }; + + conf-pull-up { + pins = "MIO22", "MIO23"; + bias-pull-up; + }; + + conf-pull-none { + pins = "MIO13", "MIO38"; + bias-disable; + }; + }; +}; + &pcie { status = "okay"; }; @@ -653,6 +936,19 @@ clock-names = "ref0", "ref1", "ref2", "ref3"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; @@ -675,22 +971,42 @@ /* SD1 with level shifter */ &sdhci1 { status = "okay"; + /* + * 1.0 revision has level shifter and this property should be + * removed for supporting UHS mode + */ no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio-bank = <1>; }; &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; +}; + +&dwc3_0 { status = "okay"; dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; }; &watchdog0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts index d9ad8a4b20d3..f7d718ff116b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -22,6 +22,7 @@ ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; + /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; /* Cleanup from RevA */ /delete-node/ ethernet-phy@21; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 5637e1c17fdf..bd8f20f3223d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -12,6 +12,7 @@ #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" #include +#include #include / { @@ -22,10 +23,13 @@ ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; + spi0 = &qspi; + usb0 = &usb0; }; chosen { @@ -59,16 +63,52 @@ &can1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; }; &dcc { status = "okay"; }; +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; @@ -85,6 +125,11 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ @@ -104,7 +149,7 @@ * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ - eeprom@54 { /* u23 */ + eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; @@ -116,20 +161,20 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; - clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ - reg = <0x6c>; - }; + /* 8T49N287 - u182 */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; - irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ - reg = <0x43>; + irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x43>; /* pmbus / i2c 0x13 */ }; - irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ - reg = <0x4d>; + irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ + compatible = "infineon,irps5401"; + reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; @@ -173,8 +218,202 @@ }; }; -&rtc { +&pinctrl0 { status = "okay"; + + pinctrl_can1_default: can1-default { + mux { + function = "can1"; + groups = "can1_6_grp"; + }; + + conf { + groups = "can1_6_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO25"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO24"; + bias-disable; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_4_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_4_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_16_grp", "gpio0_17_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_16_grp", "gpio0_17_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + }; + + pinctrl_gem3_default: gem3-default { + mux { + function = "ethernet3"; + groups = "ethernet3_0_grp"; + }; + + conf { + groups = "ethernet3_0_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", + "MIO75"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", + "MIO69"; + bias-disable; + low-power-enable; + }; + + mux-mdio { + function = "mdio3"; + groups = "mdio3_0_grp"; + }; + + conf-mdio { + groups = "mdio3_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + }; + + pinctrl_sdhci1_default: sdhci1-default { + mux { + groups = "sdio1_0_grp"; + function = "sdio1"; + }; + + conf { + groups = "sdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + drive-strength = <12>; + }; + + mux-cd { + groups = "sdio1_cd_0_grp"; + function = "sdio1_cd"; + }; + + conf-cd { + groups = "sdio1_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_uart0_default: uart0-default { + mux { + groups = "uart0_4_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_4_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO18"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO19"; + bias-disable; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_5_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_5_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO21"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO20"; + bias-disable; + }; + }; + + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + }; }; &psgtr { @@ -184,6 +423,23 @@ clock-names = "ref1", "ref2", "ref3"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + +&rtc { + status = "okay"; +}; + &sata { status = "okay"; /* SATA OOB timing settings */ @@ -203,22 +459,38 @@ &sdhci1 { status = "okay"; no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio-bank = <1>; disable-wp; }; &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; +}; + +&dwc3_0 { status = "okay"; dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; }; &watchdog0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 7f2e32831b05..96feaad30166 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -12,6 +12,7 @@ #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" #include +#include #include / { @@ -22,10 +23,13 @@ ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; + spi0 = &qspi; + usb0 = &usb0; }; chosen { @@ -64,6 +68,8 @@ &can1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; }; &dcc { @@ -106,6 +112,8 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; @@ -122,6 +130,11 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; @@ -172,9 +185,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; - clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ - reg = <0x6c>; - }; + /* 8T49N287 - u182 */ }; i2c@2 { @@ -219,18 +230,202 @@ }; }; -&qspi { +&pinctrl0 { status = "okay"; - flash@0 { - compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0>; - }; -}; -&rtc { - status = "okay"; + pinctrl_can1_default: can1-default { + mux { + function = "can1"; + groups = "can1_6_grp"; + }; + + conf { + groups = "can1_6_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO25"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO24"; + bias-disable; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_4_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_4_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_16_grp", "gpio0_17_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_16_grp", "gpio0_17_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + }; + + pinctrl_gem3_default: gem3-default { + mux { + function = "ethernet3"; + groups = "ethernet3_0_grp"; + }; + + conf { + groups = "ethernet3_0_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", + "MIO75"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", + "MIO69"; + bias-disable; + low-power-enable; + }; + + mux-mdio { + function = "mdio3"; + groups = "mdio3_0_grp"; + }; + + conf-mdio { + groups = "mdio3_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + }; + + pinctrl_sdhci1_default: sdhci1-default { + mux { + groups = "sdio1_0_grp"; + function = "sdio1"; + }; + + conf { + groups = "sdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + drive-strength = <12>; + }; + + mux-cd { + groups = "sdio1_cd_0_grp"; + function = "sdio1_cd"; + }; + + conf-cd { + groups = "sdio1_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_uart0_default: uart0-default { + mux { + groups = "uart0_4_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_4_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO18"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO19"; + bias-disable; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_5_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_5_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO21"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO20"; + bias-disable; + }; + }; + + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + }; }; &psgtr { @@ -240,6 +435,23 @@ clock-names = "ref1", "ref2", "ref3"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + +&rtc { + status = "okay"; +}; + &sata { status = "okay"; /* SATA OOB timing settings */ @@ -259,22 +471,38 @@ &sdhci1 { status = "okay"; no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio-bank = <1>; disable-wp; }; &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; +}; + +&dwc3_0 { status = "okay"; dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; }; &watchdog0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index eff7c6447087..20b7c75bb1d3 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2019, Xilinx, Inc. + * (C) Copyright 2016 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -13,6 +13,7 @@ #include "zynqmp-clk-ccf.dtsi" #include #include +#include #include / { @@ -24,10 +25,13 @@ i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; + spi0 = &qspi; + usb0 = &usb0; }; chosen { @@ -150,24 +154,14 @@ &can1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; }; &dcc { status = "okay"; }; -&zynqmp_dpdma { - status = "okay"; -}; - -&zynqmp_dpsub { - status = "okay"; - phy-names = "dp-phy0", "dp-phy1"; - phys = <&psgtr 1 PHY_TYPE_DP 0 3>, - <&psgtr 0 PHY_TYPE_DP 1 3>; -}; - -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; }; @@ -204,6 +198,8 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; @@ -215,11 +211,18 @@ &gpio { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { status = "okay"; clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; @@ -478,6 +481,11 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ @@ -652,6 +660,269 @@ }; }; +&pinctrl0 { + status = "okay"; + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_3_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_3_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_14_grp", "gpio0_15_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_14_grp", "gpio0_15_grp"; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_4_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_4_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_16_grp", "gpio0_17_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_16_grp", "gpio0_17_grp"; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_uart0_default: uart0-default { + mux { + groups = "uart0_4_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_4_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO18"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO19"; + bias-disable; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_5_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_5_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO21"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO20"; + bias-disable; + }; + }; + + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + }; + + pinctrl_gem3_default: gem3-default { + mux { + function = "ethernet3"; + groups = "ethernet3_0_grp"; + }; + + conf { + groups = "ethernet3_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", + "MIO75"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", + "MIO69"; + bias-disable; + low-power-enable; + }; + + mux-mdio { + function = "mdio3"; + groups = "mdio3_0_grp"; + }; + + conf-mdio { + groups = "mdio3_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + }; + + pinctrl_can1_default: can1-default { + mux { + function = "can1"; + groups = "can1_6_grp"; + }; + + conf { + groups = "can1_6_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO25"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO24"; + bias-disable; + }; + }; + + pinctrl_sdhci1_default: sdhci1-default { + mux { + groups = "sdio1_0_grp"; + function = "sdio1"; + }; + + conf { + groups = "sdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux-cd { + groups = "sdio1_cd_0_grp"; + function = "sdio1_cd"; + }; + + conf-cd { + groups = "sdio1_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux-wp { + groups = "sdio1_wp_0_grp"; + function = "sdio1_wp"; + }; + + conf-wp { + groups = "sdio1_wp_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_gpio_default: gpio-default { + mux { + function = "gpio0"; + groups = "gpio0_22_grp", "gpio0_23_grp"; + }; + + conf { + groups = "gpio0_22_grp", "gpio0_23_grp"; + slew-rate = ; + power-source = ; + }; + + mux-msp { + function = "gpio0"; + groups = "gpio0_13_grp", "gpio0_38_grp"; + }; + + conf-msp { + groups = "gpio0_13_grp", "gpio0_38_grp"; + slew-rate = ; + power-source = ; + }; + + conf-pull-up { + pins = "MIO22"; + bias-pull-up; + }; + + conf-pull-none { + pins = "MIO13", "MIO23", "MIO38"; + bias-disable; + }; + }; +}; + &psgtr { status = "okay"; /* nc, sata, usb3, dp */ @@ -659,6 +930,19 @@ clock-names = "ref1", "ref2", "ref3"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; @@ -681,24 +965,54 @@ /* SD1 with level shifter */ &sdhci1 { status = "okay"; + /* + * This property should be removed for supporting UHS mode + */ no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio-bank = <1>; }; &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; +}; + +&dwc3_0 { status = "okay"; dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; }; &watchdog0 { status = "okay"; }; + +&zynqmp_dpdma { + status = "okay"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 3>, + <&psgtr 0 PHY_TYPE_DP 1 3>; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index d4b68f0d0098..e36df6adbeee 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -13,6 +13,7 @@ #include "zynqmp-clk-ccf.dtsi" #include #include +#include #include / { @@ -24,9 +25,12 @@ i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; + spi0 = &qspi; + usb0 = &usb0; }; chosen { @@ -166,6 +170,8 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; @@ -177,11 +183,18 @@ &gpio { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { status = "okay"; clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; @@ -326,13 +339,16 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ + irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ + compatible = "infineon,irps5401"; reg = <0x43>; }; - irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ + irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ + compatible = "infineon,irps5401"; reg = <0x44>; }; - irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ + irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ + compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ @@ -354,6 +370,11 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; @@ -455,9 +476,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - si5382: clock-generator@69 { /* SI5382 - u48 */ - reg = <0x69>; - }; + /* SI5382 - u48 */ }; i2c@5 { #address-cells = <1>; @@ -542,13 +561,230 @@ }; }; +&pinctrl0 { + status = "okay"; + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_3_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_3_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_14_grp", "gpio0_15_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_14_grp", "gpio0_15_grp"; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_4_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_4_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_16_grp", "gpio0_17_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_16_grp", "gpio0_17_grp"; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_uart0_default: uart0-default { + mux { + groups = "uart0_4_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_4_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO18"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO19"; + bias-disable; + }; + }; + + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + }; + + pinctrl_gem3_default: gem3-default { + mux { + function = "ethernet3"; + groups = "ethernet3_0_grp"; + }; + + conf { + groups = "ethernet3_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", + "MIO75"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", + "MIO69"; + bias-disable; + low-power-enable; + }; + + mux-mdio { + function = "mdio3"; + groups = "mdio3_0_grp"; + }; + + conf-mdio { + groups = "mdio3_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + }; + + pinctrl_sdhci1_default: sdhci1-default { + mux { + groups = "sdio1_0_grp"; + function = "sdio1"; + }; + + conf { + groups = "sdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux-cd { + groups = "sdio1_cd_0_grp"; + function = "sdio1_cd"; + }; + + conf-cd { + groups = "sdio1_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + }; + + pinctrl_gpio_default: gpio-default { + mux { + function = "gpio0"; + groups = "gpio0_22_grp", "gpio0_23_grp"; + }; + + conf { + groups = "gpio0_22_grp", "gpio0_23_grp"; + slew-rate = ; + power-source = ; + }; + + mux-msp { + function = "gpio0"; + groups = "gpio0_13_grp", "gpio0_38_grp"; + }; + + conf-msp { + groups = "gpio0_13_grp", "gpio0_38_grp"; + slew-rate = ; + power-source = ; + }; + + conf-pull-up { + pins = "MIO22"; + bias-pull-up; + }; + + conf-pull-none { + pins = "MIO13", "MIO23", "MIO38"; + bias-disable; + }; + }; +}; + &psgtr { status = "okay"; - /* nc, sata, usb3, dp */ - clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; + /* nc, dp, usb3, sata */ + clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref1", "ref2", "ref3"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; @@ -565,24 +801,42 @@ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; - phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; + phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1_default>; + disable-wp; + /* + * This property should be removed for supporting UHS mode + */ no-1-8-v; xlnx,mio-bank = <1>; }; &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; +}; + +&dwc3_0 { status = "okay"; dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; }; &zynqmp_dpdma { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 28dccb891a53..74e66443e4ce 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2019, Xilinx, Inc. + * (C) Copyright 2014 - 2021, Xilinx, Inc. * * Michal Simek * @@ -156,21 +156,6 @@ mbox-names = "tx", "rx"; }; - zynqmp_clk: clock-controller { - #clock-cells = <1>; - compatible = "xlnx,zynqmp-clk"; - clocks = <&pss_ref_clk>, - <&video_clk>, - <&pss_alt_ref_clk>, - <&aux_ref_clk>, - <>_crx_ref_clk>; - clock-names = "pss_ref_clk", - "video_clk", - "pss_alt_ref_clk", - "aux_ref_clk", - "gt_crx_ref_clk"; - }; - nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; @@ -193,6 +178,11 @@ compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; + + pinctrl0: pinctrl { + compatible = "xlnx,zynqmp-pinctrl"; + status = "disabled"; + }; }; }; @@ -245,6 +235,7 @@ cci: cci@fd6e0000 { compatible = "arm,cci-400"; + status = "disabled"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; @@ -630,6 +621,8 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; + #stream-id-cells = <1>; + iommus = <&smmu 0x4d0>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; @@ -670,7 +663,7 @@ interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; - calibration = <0x8000>; + calibration = <0x7FFF>; }; sata: ahci@fd0c0000 { @@ -680,6 +673,7 @@ interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; + resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; @@ -792,7 +786,7 @@ }; uart0: serial@ff000000 { - compatible = "cdns,uart-r1p12", "xlnx,xuartps"; + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; @@ -802,7 +796,7 @@ }; uart1: serial@ff010000 { - compatible = "cdns,uart-r1p12", "xlnx,xuartps"; + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; @@ -811,24 +805,58 @@ power-domains = <&zynqmp_firmware PD_UART_1>; }; - usb0: usb@fe200000 { - compatible = "snps,dwc3"; + usb0: usb@ff9d0000 { + #address-cells = <2>; + #size-cells = <2>; status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 65 4>; - reg = <0x0 0xfe200000 0x0 0x40000>; - clock-names = "clk_xin", "clk_ahb"; + compatible = "xlnx,zynqmp-dwc3"; + reg = <0x0 0xff9d0000 0x0 0x100>; + clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; + reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; + ranges; + + dwc3_0: usb@fe200000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe200000 0x0 0x40000>; + interrupt-parent = <&gic>; + interrupt-names = "dwc_usb3", "otg"; + interrupts = <0 65 4>, <0 69 4>; + #stream-id-cells = <1>; + iommus = <&smmu 0x860>; + snps,quirk-frame-length-adjustment = <0x20>; + /* dma-coherent; */ + }; }; - usb1: usb@fe300000 { - compatible = "snps,dwc3"; + usb1: usb@ff9e0000 { + #address-cells = <2>; + #size-cells = <2>; status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 70 4>; - reg = <0x0 0xfe300000 0x0 0x40000>; - clock-names = "clk_xin", "clk_ahb"; + compatible = "xlnx,zynqmp-dwc3"; + reg = <0x0 0xff9e0000 0x0 0x100>; + clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; + reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; + ranges; + + dwc3_1: usb@fe300000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe300000 0x0 0x40000>; + interrupt-parent = <&gic>; + interrupt-names = "dwc_usb3", "otg"; + interrupts = <0 70 4>, <0 74 4>; + #stream-id-cells = <1>; + iommus = <&smmu 0x861>; + snps,quirk-frame-length-adjustment = <0x20>; + /* dma-coherent; */ + }; }; watchdog0: watchdog@fd4d0000 { @@ -837,7 +865,8 @@ interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; - timeout-sec = <10>; + timeout-sec = <60>; + reset-on-timeout; }; lpd_watchdog: watchdog@ff150000 {