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drm/i915: Fix cs timestamp frequency for cl/bw

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Despite what the spec says the TIMESTAMP register seems to
tick once every hrawclk (confirmed on i965gm and g35).

v2: Rebase

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221031135703.14670-4-ville.syrjala@linux.intel.com
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Ville Syrjälä 2022-10-31 15:57:00 +02:00
parent 78e418d0ea
commit dbea79a502
1 changed files with 3 additions and 1 deletions
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4
drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
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@ -147,8 +147,10 @@ static u32 gen4_read_clock_frequency(struct intel_uncore *uncore)
* "The value in this register increments once every 16
* hclks." (through the “Clocking Configuration”
* (“CLKCFG”) MCHBAR register)
*
* Testing on actual hardware has shown there is no /16.
*/
return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000;
}
static u32 read_clock_frequency(struct intel_uncore *uncore)