dt-bindings: watchdog: Convert Xilinx watchdog bindings to json-schema

Convert Xilinx watchdog bindings to DT schema format using json-schema

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20220818150637.815-1-srinivas.neeli@xilinx.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
This commit is contained in:
Srinivas Neeli 2022-08-18 20:36:37 +05:30 committed by Wim Van Sebroeck
parent 19f04459f0
commit dc1f12b916
2 changed files with 68 additions and 26 deletions

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Xilinx AXI/PLB soft-core watchdog Device Tree Bindings
---------------------------------------------------------
Required properties:
- compatible : Should be "xlnx,xps-timebase-wdt-1.00.a" or
"xlnx,xps-timebase-wdt-1.01.a".
- reg : Physical base address and size
Optional properties:
- clocks : Input clock specifier. Refer to common clock
bindings.
- clock-frequency : Frequency of clock in Hz
- xlnx,wdt-enable-once : 0 - Watchdog can be restarted
1 - Watchdog can be enabled just once
- xlnx,wdt-interval : Watchdog timeout interval in 2^<val> clock cycles,
<val> is integer from 8 to 31.
Example:
axi-timebase-wdt@40100000 {
clock-frequency = <50000000>;
compatible = "xlnx,xps-timebase-wdt-1.00.a";
clocks = <&clkc 15>;
reg = <0x40100000 0x10000>;
xlnx,wdt-enable-once = <0x0>;
xlnx,wdt-interval = <0x1b>;
} ;

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# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx AXI/PLB softcore and window Watchdog Timer
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
- Srinivas Neeli <srinivas.neeli@xilinx.com>
description:
The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
WDT uses a dual-expiration architecture. After one expiration of
the timeout interval, an interrupt is generated and the WDT state
bit is set to one in the status register. If the state bit is not
cleared (by writing a one to the state bit) before the next
expiration of the timeout interval, a WDT reset is generated.
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
enum:
- xlnx,xps-timebase-wdt-1.01.a
- xlnx,xps-timebase-wdt-1.00.a
reg:
maxItems: 1
clocks:
maxItems: 1
clock-frequency:
description: Frequency of clock in Hz
xlnx,wdt-interval:
$ref: /schemas/types.yaml#/definitions/uint32
description: Watchdog timeout interval
minimum: 8
maximum: 32
xlnx,wdt-enable-once:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: If watchdog is configured as enable once,
then the watchdog cannot be disabled after
it has been enabled.
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
watchdog@40100000 {
compatible = "xlnx,xps-timebase-wdt-1.00.a";
reg = <0x40100000 0x1000>;
clock-frequency = <50000000>;
clocks = <&clkc 15>;
xlnx,wdt-enable-once = <0x0>;
xlnx,wdt-interval = <0x1b>;
};
...