drm/i915: Move dsc rate params compute into drm
The function intel_compute_rc_parameters is part of the dsc spec and is not driver-specific. Other drm drivers might like to use it. The function is not changed; just moved and renamed. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: David Francis <David.Francis@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190221202001.28430-2-David.Francis@amd.com
This commit is contained in:
David Francis
Harry Wentland
parent
8ff62645ea
commit
dc43332b7a
@ -11,6 +11,7 @@
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/byteorder/generic.h>
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#include <drm/drm_print.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_dsc.h>
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@ -244,3 +245,137 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
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/* PPS 94 - 127 are O */
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}
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EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
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/**
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* drm_dsc_compute_rc_parameters() - Write rate control
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* parameters to the dsc configuration defined in
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* &struct drm_dsc_config in accordance with the DSC 1.1
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* specification. Some configuration fields must be present
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* beforehand.
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*
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* @vdsc_cfg:
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* DSC Configuration data partially filled by driver
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*/
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int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
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{
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unsigned long groups_per_line = 0;
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unsigned long groups_total = 0;
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unsigned long num_extra_mux_bits = 0;
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unsigned long slice_bits = 0;
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unsigned long hrd_delay = 0;
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unsigned long final_scale = 0;
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unsigned long rbs_min = 0;
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/* Number of groups used to code each line of a slice */
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groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
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DSC_RC_PIXELS_PER_GROUP);
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/* chunksize in Bytes */
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vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
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vdsc_cfg->bits_per_pixel,
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(8 * 16));
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if (vdsc_cfg->convert_rgb)
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num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
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(4 * vdsc_cfg->bits_per_component + 4)
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- 2);
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else
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num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
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(4 * vdsc_cfg->bits_per_component + 4) +
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2 * (4 * vdsc_cfg->bits_per_component) - 2;
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/* Number of bits in one Slice */
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slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
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while ((num_extra_mux_bits > 0) &&
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((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
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num_extra_mux_bits--;
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if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
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vdsc_cfg->initial_scale_value = groups_per_line + 8;
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/* scale_decrement_interval calculation according to DSC spec 1.11 */
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if (vdsc_cfg->initial_scale_value > 8)
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vdsc_cfg->scale_decrement_interval = groups_per_line /
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(vdsc_cfg->initial_scale_value - 8);
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else
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vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
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vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
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(vdsc_cfg->initial_xmit_delay *
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vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
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if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
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DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
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return -ERANGE;
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}
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final_scale = (vdsc_cfg->rc_model_size * 8) /
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(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
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if (vdsc_cfg->slice_height > 1)
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/*
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* NflBpgOffset is 16 bit value with 11 fractional bits
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* hence we multiply by 2^11 for preserving the
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* fractional part
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*/
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vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
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(vdsc_cfg->slice_height - 1));
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else
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vdsc_cfg->nfl_bpg_offset = 0;
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/* 2^16 - 1 */
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if (vdsc_cfg->nfl_bpg_offset > 65535) {
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DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
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return -ERANGE;
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}
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/* Number of groups used to code the entire slice */
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groups_total = groups_per_line * vdsc_cfg->slice_height;
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/* slice_bpg_offset is 16 bit value with 11 fractional bits */
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vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
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vdsc_cfg->initial_offset +
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num_extra_mux_bits) << 11),
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groups_total);
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if (final_scale > 9) {
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/*
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* ScaleIncrementInterval =
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* finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
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* as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
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* we need divide by 2^11 from pstDscCfg values
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*/
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vdsc_cfg->scale_increment_interval =
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(vdsc_cfg->final_offset * (1 << 11)) /
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((vdsc_cfg->nfl_bpg_offset +
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vdsc_cfg->slice_bpg_offset) *
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(final_scale - 9));
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} else {
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/*
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* If finalScaleValue is less than or equal to 9, a value of 0 should
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* be used to disable the scale increment at the end of the slice
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*/
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vdsc_cfg->scale_increment_interval = 0;
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}
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if (vdsc_cfg->scale_increment_interval > 65535) {
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DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n");
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return -ERANGE;
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}
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/*
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* DSC spec mentions that bits_per_pixel specifies the target
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* bits/pixel (bpp) rate that is used by the encoder,
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* in steps of 1/16 of a bit per pixel
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*/
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rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
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DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
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vdsc_cfg->bits_per_pixel, 16) +
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groups_per_line * vdsc_cfg->first_line_bpg_offset;
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hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
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vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
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vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
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return 0;
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}
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EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);
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@ -317,129 +317,6 @@ static int get_column_index_for_rc_params(u8 bits_per_component)
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}
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}
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static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
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{
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unsigned long groups_per_line = 0;
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unsigned long groups_total = 0;
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unsigned long num_extra_mux_bits = 0;
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unsigned long slice_bits = 0;
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unsigned long hrd_delay = 0;
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unsigned long final_scale = 0;
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unsigned long rbs_min = 0;
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/* Number of groups used to code each line of a slice */
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groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
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DSC_RC_PIXELS_PER_GROUP);
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/* chunksize in Bytes */
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vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
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vdsc_cfg->bits_per_pixel,
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(8 * 16));
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if (vdsc_cfg->convert_rgb)
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num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
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(4 * vdsc_cfg->bits_per_component + 4)
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- 2);
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else
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num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
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(4 * vdsc_cfg->bits_per_component + 4) +
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2 * (4 * vdsc_cfg->bits_per_component) - 2;
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/* Number of bits in one Slice */
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slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
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while ((num_extra_mux_bits > 0) &&
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((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
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num_extra_mux_bits--;
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if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
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vdsc_cfg->initial_scale_value = groups_per_line + 8;
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/* scale_decrement_interval calculation according to DSC spec 1.11 */
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if (vdsc_cfg->initial_scale_value > 8)
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vdsc_cfg->scale_decrement_interval = groups_per_line /
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(vdsc_cfg->initial_scale_value - 8);
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else
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vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
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vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
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(vdsc_cfg->initial_xmit_delay *
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vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
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if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
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DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
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return -ERANGE;
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}
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final_scale = (vdsc_cfg->rc_model_size * 8) /
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(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
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if (vdsc_cfg->slice_height > 1)
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/*
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* NflBpgOffset is 16 bit value with 11 fractional bits
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* hence we multiply by 2^11 for preserving the
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* fractional part
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*/
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vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
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(vdsc_cfg->slice_height - 1));
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else
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vdsc_cfg->nfl_bpg_offset = 0;
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/* 2^16 - 1 */
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if (vdsc_cfg->nfl_bpg_offset > 65535) {
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DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
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return -ERANGE;
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}
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/* Number of groups used to code the entire slice */
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groups_total = groups_per_line * vdsc_cfg->slice_height;
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/* slice_bpg_offset is 16 bit value with 11 fractional bits */
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vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
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vdsc_cfg->initial_offset +
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num_extra_mux_bits) << 11),
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groups_total);
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if (final_scale > 9) {
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/*
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* ScaleIncrementInterval =
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* finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
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* as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
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* we need divide by 2^11 from pstDscCfg values
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*/
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vdsc_cfg->scale_increment_interval =
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(vdsc_cfg->final_offset * (1 << 11)) /
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((vdsc_cfg->nfl_bpg_offset +
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vdsc_cfg->slice_bpg_offset) *
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(final_scale - 9));
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} else {
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/*
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* If finalScaleValue is less than or equal to 9, a value of 0 should
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* be used to disable the scale increment at the end of the slice
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*/
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vdsc_cfg->scale_increment_interval = 0;
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}
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if (vdsc_cfg->scale_increment_interval > 65535) {
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DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n");
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return -ERANGE;
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}
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/*
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* DSC spec mentions that bits_per_pixel specifies the target
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* bits/pixel (bpp) rate that is used by the encoder,
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* in steps of 1/16 of a bit per pixel
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*/
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rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
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DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
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vdsc_cfg->bits_per_pixel, 16) +
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groups_per_line * vdsc_cfg->first_line_bpg_offset;
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hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
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vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
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vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
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return 0;
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}
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int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
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struct intel_crtc_state *pipe_config)
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{
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@ -574,7 +451,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
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vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
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(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
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return intel_compute_rc_parameters(vdsc_cfg);
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return drm_dsc_compute_rc_parameters(vdsc_cfg);
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}
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enum intel_display_power_domain
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@ -604,5 +604,6 @@ struct drm_dsc_pps_infoframe {
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void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp);
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void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
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const struct drm_dsc_config *dsc_cfg);
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int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
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#endif /* _DRM_DSC_H_ */
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