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riscv: Fixup obvious bug for fp-regs reset

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CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine
ISA Register misa. Every bit:1 indicate a feature, so we should beqz
reset_done when there is no F/D bit in csr_misa register.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
[paul.walmsley@sifive.com: fix typo in commit message]
Fixes: 9e80635619 ("riscv: clear the instruction cache and all registers when booting")
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
This commit is contained in:
Guo Ren 2020-01-05 10:52:14 +08:00 committed by Paul Walmsley
parent 13cf4cf030
commit dc6fcba72f
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/kernel/head.S
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@ -251,7 +251,7 @@ ENTRY(reset_regs)
#ifdef CONFIG_FPU
csrr t0, CSR_MISA
andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
bnez t0, .Lreset_regs_done
beqz t0, .Lreset_regs_done
li t1, SR_FS
csrs CSR_STATUS, t1