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staging: rtl8192e: Join constants Rtl819XAGCTAB_.. with ..PciEAGCTAB..

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Join constants Rtl819XAGCTAB_Array with Rtl8192PciEAGCTAB_Array to
RTL8192E_AGCTAB_ARR to improve readability.

Signed-off-by: Philipp Hortmann <philipp.g.hortmann@gmail.com>
Link: https://lore.kernel.org/r/c7ca930adb5f72daa61b15b02001d09c4a1f8f46.1678814935.git.philipp.g.hortmann@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Philipp Hortmann 2023-03-14 19:44:13 +01:00 committed by Greg Kroah-Hartman
parent 22fc1bb475
commit dc756b9354
4 changed files with 3 additions and 4 deletions
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2
drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c
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@ -313,7 +313,7 @@ static void _rtl92e_phy_config_bb(struct net_device *dev, u8 ConfigType)
struct r8192_priv *priv = rtllib_priv(dev);
AGCTAB_ArrayLen = RTL8192E_AGCTAB_ARR_LEN;
Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
Rtl819XAGCTAB_Array_Table = RTL8192E_AGCTAB_ARR;
if (priv->rf_type == RF_1T2R) {
PHY_REGArrayLen = RTL8192E_PHY_REG_1T2R_ARR_LEN;
Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;

1
drivers/staging/rtl8192e/rtl8192e/r8192E_phy.h
View File

@ -9,7 +9,6 @@
#define MAX_DOZE_WAITING_TIMES_9x 64
#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array
#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
extern u32 rtl819XAGCTAB_Array[];

2
drivers/staging/rtl8192e/rtl8192e/table.c
View File

@ -347,7 +347,7 @@ u32 RTL8192E_MACPHY_ARR_PG[] = {
0x318, 0x00000fff, 0x00000800,
};
u32 Rtl8192PciEAGCTAB_Array[RTL8192E_AGCTAB_ARR_LEN] = {
u32 RTL8192E_AGCTAB_ARR[RTL8192E_AGCTAB_ARR_LEN] = {
0xc78, 0x7d000001,
0xc78, 0x7d010001,
0xc78, 0x7d020001,

2
drivers/staging/rtl8192e/rtl8192e/table.h
View File

@ -22,6 +22,6 @@ extern u32 RTL8192E_MACPHY_ARR[RTL8192E_MACPHY_ARR_LEN];
#define RTL8192E_MACPHY_ARR_PG_LEN 30
extern u32 RTL8192E_MACPHY_ARR_PG[RTL8192E_MACPHY_ARR_PG_LEN];
#define RTL8192E_AGCTAB_ARR_LEN 384
extern u32 Rtl8192PciEAGCTAB_Array[RTL8192E_AGCTAB_ARR_LEN];
extern u32 RTL8192E_AGCTAB_ARR[RTL8192E_AGCTAB_ARR_LEN];
#endif