Merge branch 'marvell10g-phy-updates'
Russell King says: ==================== marvell10g updates This series: - adds MDI/MDIX reporting - adds support for 10/100Mbps half-duplex link modes - adds a comment describing the setup on VF610 ZII boards (where the phy interface mode doesn't change.) - cleans up the phy interace mode switching ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
dc917aec77
@ -6,12 +6,18 @@
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*
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* There appears to be several different data paths through the PHY which
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* are automatically managed by the PHY. The following has been determined
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* via observation and experimentation:
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* via observation and experimentation for a setup using single-lane Serdes:
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*
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* SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
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* 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
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* 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
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*
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* With XAUI, observation shows:
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*
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* XAUI PHYXS -- <appropriate PCS as above>
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*
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* and no switching of the host interface mode occurs.
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*
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* If both the fiber and copper ports are connected, the first to gain
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* link takes priority and the other port is completely locked out.
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*/
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@ -23,19 +29,17 @@ enum {
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MV_PCS_BASE_R = 0x1000,
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MV_PCS_1000BASEX = 0x2000,
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MV_PCS_PAIRSWAP = 0x8182,
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MV_PCS_PAIRSWAP_MASK = 0x0003,
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MV_PCS_PAIRSWAP_AB = 0x0002,
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MV_PCS_PAIRSWAP_NONE = 0x0003,
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/* These registers appear at 0x800X and 0xa00X - the 0xa00X control
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* registers appear to set themselves to the 0x800X when AN is
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* restarted, but status registers appear readable from either.
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*/
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MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
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MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
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/* This register appears to reflect the copper status */
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MV_AN_RESULT = 0xa016,
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MV_AN_RESULT_SPD_10 = BIT(12),
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MV_AN_RESULT_SPD_100 = BIT(13),
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MV_AN_RESULT_SPD_1000 = BIT(14),
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MV_AN_RESULT_SPD_10000 = BIT(15),
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};
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static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
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@ -149,12 +153,18 @@ static int mv3310_config_init(struct phy_device *phydev)
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if (val & MDIO_PMA_EXTABLE_1000BKX)
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__set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
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supported);
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if (val & MDIO_PMA_EXTABLE_100BTX)
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if (val & MDIO_PMA_EXTABLE_100BTX) {
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__set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
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supported);
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if (val & MDIO_PMA_EXTABLE_10BT)
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__set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
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supported);
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}
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if (val & MDIO_PMA_EXTABLE_10BT) {
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__set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
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supported);
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__set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
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supported);
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}
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}
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if (!ethtool_convert_link_mode_to_legacy_u32(&mask, supported))
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@ -174,6 +184,9 @@ static int mv3310_config_aneg(struct phy_device *phydev)
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u32 advertising;
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int ret;
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/* We don't support manual MDI control */
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phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
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if (phydev->autoneg == AUTONEG_DISABLE) {
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ret = genphy_c45_pma_setup_forced(phydev);
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if (ret < 0)
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@ -232,6 +245,24 @@ static int mv3310_aneg_done(struct phy_device *phydev)
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return genphy_c45_aneg_done(phydev);
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}
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static void mv3310_update_interface(struct phy_device *phydev)
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{
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if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
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phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
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/* The PHY automatically switches its serdes interface (and
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* active PHYXS instance) between Cisco SGMII and 10GBase-KR
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* modes according to the speed. Florian suggests setting
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* phydev->interface to communicate this to the MAC. Only do
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* this if we are already in either SGMII or 10GBase-KR mode.
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*/
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if (phydev->speed == SPEED_10000)
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phydev->interface = PHY_INTERFACE_MODE_10GKR;
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else if (phydev->speed >= SPEED_10 &&
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phydev->speed < SPEED_10000)
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phydev->interface = PHY_INTERFACE_MODE_SGMII;
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}
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}
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/* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
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static int mv3310_read_10gbr_status(struct phy_device *phydev)
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{
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@ -239,8 +270,7 @@ static int mv3310_read_10gbr_status(struct phy_device *phydev)
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phydev->speed = SPEED_10000;
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phydev->duplex = DUPLEX_FULL;
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if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
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phydev->interface = PHY_INTERFACE_MODE_10GKR;
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mv3310_update_interface(phydev);
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return 0;
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}
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@ -263,6 +293,7 @@ static int mv3310_read_status(struct phy_device *phydev)
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phydev->link = 0;
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phydev->pause = 0;
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phydev->asym_pause = 0;
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phydev->mdix = 0;
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val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
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if (val < 0)
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@ -293,22 +324,8 @@ static int mv3310_read_status(struct phy_device *phydev)
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phydev->lp_advertising |= mii_stat1000_to_ethtool_lpa_t(val);
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if (phydev->autoneg == AUTONEG_ENABLE) {
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_RESULT);
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if (val < 0)
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return val;
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if (val & MV_AN_RESULT_SPD_10000)
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phydev->speed = SPEED_10000;
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else if (val & MV_AN_RESULT_SPD_1000)
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phydev->speed = SPEED_1000;
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else if (val & MV_AN_RESULT_SPD_100)
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phydev->speed = SPEED_100;
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else if (val & MV_AN_RESULT_SPD_10)
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phydev->speed = SPEED_10;
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phydev->duplex = DUPLEX_FULL;
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}
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if (phydev->autoneg == AUTONEG_ENABLE)
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phy_resolve_aneg_linkmode(phydev);
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}
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if (phydev->autoneg != AUTONEG_ENABLE) {
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@ -317,21 +334,30 @@ static int mv3310_read_status(struct phy_device *phydev)
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return val;
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}
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if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
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phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
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/* The PHY automatically switches its serdes interface (and
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* active PHYXS instance) between Cisco SGMII and 10GBase-KR
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* modes according to the speed. Florian suggests setting
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* phydev->interface to communicate this to the MAC. Only do
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* this if we are already in either SGMII or 10GBase-KR mode.
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*/
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if (phydev->speed == SPEED_10000)
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phydev->interface = PHY_INTERFACE_MODE_10GKR;
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else if (phydev->speed >= SPEED_10 &&
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phydev->speed < SPEED_10000)
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phydev->interface = PHY_INTERFACE_MODE_SGMII;
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if (phydev->speed == SPEED_10000) {
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val = genphy_c45_read_mdix(phydev);
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if (val < 0)
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return val;
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} else {
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val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP);
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if (val < 0)
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return val;
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switch (val & MV_PCS_PAIRSWAP_MASK) {
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case MV_PCS_PAIRSWAP_AB:
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phydev->mdix = ETH_TP_MDI_X;
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break;
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case MV_PCS_PAIRSWAP_NONE:
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phydev->mdix = ETH_TP_MDI;
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break;
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default:
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phydev->mdix = ETH_TP_MDI_INVALID;
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break;
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}
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}
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mv3310_update_interface(phydev);
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return 0;
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}
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@ -341,7 +367,9 @@ static struct phy_driver mv3310_drivers[] = {
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.phy_id_mask = MARVELL_PHY_ID_MASK,
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.name = "mv88x3310",
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.features = SUPPORTED_10baseT_Full |
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SUPPORTED_10baseT_Half |
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SUPPORTED_100baseT_Full |
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SUPPORTED_100baseT_Half |
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SUPPORTED_1000baseT_Full |
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SUPPORTED_Autoneg |
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SUPPORTED_TP |
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@ -233,6 +233,39 @@ int genphy_c45_read_pma(struct phy_device *phydev)
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}
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EXPORT_SYMBOL_GPL(genphy_c45_read_pma);
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/**
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* genphy_c45_read_mdix - read mdix status from PMA
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* @phydev: target phy_device struct
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*/
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int genphy_c45_read_mdix(struct phy_device *phydev)
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{
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int val;
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if (phydev->speed == SPEED_10000) {
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val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
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MDIO_PMA_10GBT_SWAPPOL);
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if (val < 0)
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return val;
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switch (val) {
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case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:
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phydev->mdix = ETH_TP_MDI;
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break;
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case 0:
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phydev->mdix = ETH_TP_MDI_X;
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break;
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default:
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phydev->mdix = ETH_TP_MDI_INVALID;
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break;
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}
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(genphy_c45_read_mdix);
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/* The gen10g_* functions are the old Clause 45 stub */
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static int gen10g_config_aneg(struct phy_device *phydev)
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@ -189,6 +189,49 @@ size_t phy_speeds(unsigned int *speeds, size_t size,
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return count;
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}
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/**
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* phy_resolve_aneg_linkmode - resolve the advertisments into phy settings
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* @phydev: The phy_device struct
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*
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* Resolve our and the link partner advertisments into their corresponding
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* speed and duplex. If full duplex was negotiated, extract the pause mode
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* from the link partner mask.
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*/
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void phy_resolve_aneg_linkmode(struct phy_device *phydev)
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{
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u32 common = phydev->lp_advertising & phydev->advertising;
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if (common & ADVERTISED_10000baseT_Full) {
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phydev->speed = SPEED_10000;
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phydev->duplex = DUPLEX_FULL;
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} else if (common & ADVERTISED_1000baseT_Full) {
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phydev->speed = SPEED_1000;
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phydev->duplex = DUPLEX_FULL;
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} else if (common & ADVERTISED_1000baseT_Half) {
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phydev->speed = SPEED_1000;
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phydev->duplex = DUPLEX_HALF;
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} else if (common & ADVERTISED_100baseT_Full) {
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phydev->speed = SPEED_100;
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phydev->duplex = DUPLEX_FULL;
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} else if (common & ADVERTISED_100baseT_Half) {
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phydev->speed = SPEED_100;
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phydev->duplex = DUPLEX_HALF;
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} else if (common & ADVERTISED_10baseT_Full) {
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phydev->speed = SPEED_10;
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phydev->duplex = DUPLEX_FULL;
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} else if (common & ADVERTISED_10baseT_Half) {
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phydev->speed = SPEED_10;
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phydev->duplex = DUPLEX_HALF;
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}
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if (phydev->duplex == DUPLEX_FULL) {
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phydev->pause = !!(phydev->lp_advertising & ADVERTISED_Pause);
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phydev->asym_pause = !!(phydev->lp_advertising &
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ADVERTISED_Asym_Pause);
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}
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}
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EXPORT_SYMBOL_GPL(phy_resolve_aneg_linkmode);
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static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad,
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u16 regnum)
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{
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@ -690,6 +690,8 @@ phy_lookup_setting(int speed, int duplex, const unsigned long *mask,
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size_t phy_speeds(unsigned int *speeds, size_t size,
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unsigned long *mask, size_t maxbit);
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void phy_resolve_aneg_linkmode(struct phy_device *phydev);
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/**
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* phy_read_mmd - Convenience function for reading a register
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* from an MMD on a given PHY.
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@ -901,6 +903,7 @@ int genphy_c45_read_lpa(struct phy_device *phydev);
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int genphy_c45_read_pma(struct phy_device *phydev);
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int genphy_c45_pma_setup_forced(struct phy_device *phydev);
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int genphy_c45_an_disable_aneg(struct phy_device *phydev);
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int genphy_c45_read_mdix(struct phy_device *phydev);
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static inline int phy_read_status(struct phy_device *phydev)
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{
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