drm/radeon: refactor set_page chipset interface v5
Cleanup the interface in preparation for hierarchical page tables.
v2: add incr parameter to set_page for simple scattered PTs uptates
added PDE-specific flags to r600_flags and radeon_drm.h
removed superfluous value masking with 0xffffffff
v3: removed superfluous bo_va->valid checking
changed R600_PTE_VALID to R600_ENTRY_VALID to handle PDE too
v4 (ck): fix indention style, rework and fix typos in commit message,
add documentation for incr parameter, also use incr
parameter for system pages
v5 (agd5f): use upper_32_bits() and minor white space fixes
Signed-off-by: Christian König <deathsimple@vodafone.de>
Signed-off-by: Dmitry Cherkassov <Dmitrii.Cherkasov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König
Alex Deucher
parent
af026c5bd1
commit
dce34bfd63
@ -1497,7 +1497,7 @@ void cayman_vm_fini(struct radeon_device *rdev)
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{
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}
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#define R600_PTE_VALID (1 << 0)
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#define R600_ENTRY_VALID (1 << 0)
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#define R600_PTE_SYSTEM (1 << 1)
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#define R600_PTE_SNOOPED (1 << 2)
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#define R600_PTE_READABLE (1 << 5)
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@ -1506,8 +1506,7 @@ void cayman_vm_fini(struct radeon_device *rdev)
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uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
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{
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uint32_t r600_flags = 0;
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r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
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r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0;
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r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
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r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
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if (flags & RADEON_VM_PAGE_SYSTEM) {
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@ -1521,30 +1520,40 @@ uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
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* cayman_vm_set_page - update the page tables using the CP
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*
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* @rdev: radeon_device pointer
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* @pe: addr of the page entry
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: access flags
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*
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* Update the page tables using the CP (cayman-si).
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*/
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void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm,
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unsigned pfn, struct ttm_mem_reg *mem,
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unsigned npages, uint32_t flags)
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void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags)
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{
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struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
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uint64_t addr, pt = vm->pt_gpu_addr + pfn * 8;
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uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
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int i;
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addr = flags = cayman_vm_page_flags(rdev, flags);
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radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, 1 + count * 2));
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radeon_ring_write(ring, pe);
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radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
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for (i = 0; i < count; ++i) {
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uint64_t value = 0;
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if (flags & RADEON_VM_PAGE_SYSTEM) {
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value = radeon_vm_map_gart(rdev, addr);
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value &= 0xFFFFFFFFFFFFF000ULL;
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addr += incr;
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radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, 1 + npages * 2));
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radeon_ring_write(ring, pt & 0xffffffff);
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radeon_ring_write(ring, (pt >> 32) & 0xff);
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for (i = 0; i < npages; ++i) {
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if (mem) {
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addr = radeon_vm_get_addr(rdev, mem, i);
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addr = addr & 0xFFFFFFFFFFFFF000ULL;
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addr |= flags;
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} else if (flags & RADEON_VM_PAGE_VALID) {
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value = addr;
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addr += incr;
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}
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radeon_ring_write(ring, addr & 0xffffffff);
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radeon_ring_write(ring, (addr >> 32) & 0xffffffff);
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value |= r600_flags;
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radeon_ring_write(ring, value);
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radeon_ring_write(ring, upper_32_bits(value));
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}
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}
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@ -1141,9 +1141,9 @@ struct radeon_asic {
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void (*fini)(struct radeon_device *rdev);
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u32 pt_ring_index;
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void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
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unsigned pfn, struct ttm_mem_reg *mem,
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unsigned npages, uint32_t flags);
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void (*set_page)(struct radeon_device *rdev, uint64_t pe,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags);
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} vm;
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/* ring specific callbacks */
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struct {
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@ -1757,7 +1757,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
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#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
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#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
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#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
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#define radeon_asic_vm_set_page(rdev, v, pfn, mem, npages, flags) (rdev)->asic->vm.set_page((rdev), (v), (pfn), (mem), (npages), (flags))
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#define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags)))
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#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
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#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
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#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
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@ -1843,9 +1843,7 @@ struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
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void radeon_vm_fence(struct radeon_device *rdev,
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struct radeon_vm *vm,
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struct radeon_fence *fence);
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u64 radeon_vm_get_addr(struct radeon_device *rdev,
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struct ttm_mem_reg *mem,
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unsigned pfn);
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uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
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int radeon_vm_bo_update_pte(struct radeon_device *rdev,
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struct radeon_vm *vm,
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struct radeon_bo *bo,
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@ -444,9 +444,9 @@ int cayman_vm_init(struct radeon_device *rdev);
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void cayman_vm_fini(struct radeon_device *rdev);
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void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ib *ib);
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uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
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void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm,
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unsigned pfn, struct ttm_mem_reg *mem,
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unsigned npages, uint32_t flags);
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void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags);
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int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
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/* DCE6 - SI */
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@ -822,42 +822,26 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev,
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}
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/**
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* radeon_vm_get_addr - get the physical address of the page
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* radeon_vm_map_gart - get the physical address of a gart page
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*
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* @rdev: radeon_device pointer
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* @mem: ttm mem
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* @pfn: pfn
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* @addr: the unmapped addr
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*
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* Look up the physical address of the page that the pte resolves
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* to (cayman+).
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* Returns the physical address of the page.
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*/
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u64 radeon_vm_get_addr(struct radeon_device *rdev,
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struct ttm_mem_reg *mem,
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unsigned pfn)
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uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)
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{
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u64 addr = 0;
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uint64_t result;
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switch (mem->mem_type) {
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case TTM_PL_VRAM:
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addr = (mem->start << PAGE_SHIFT);
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addr += pfn * RADEON_GPU_PAGE_SIZE;
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addr += rdev->vm_manager.vram_base_offset;
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break;
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case TTM_PL_TT:
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/* offset inside page table */
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addr = mem->start << PAGE_SHIFT;
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addr += pfn * RADEON_GPU_PAGE_SIZE;
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addr = addr >> PAGE_SHIFT;
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/* page table offset */
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addr = rdev->gart.pages_addr[addr];
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/* in case cpu page size != gpu page size*/
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addr += (pfn * RADEON_GPU_PAGE_SIZE) & (~PAGE_MASK);
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break;
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default:
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break;
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}
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return addr;
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/* page table offset */
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result = rdev->gart.pages_addr[addr >> PAGE_SHIFT];
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/* in case cpu page size != gpu page size*/
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result |= addr & (~PAGE_MASK);
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return result;
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}
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/**
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@ -883,7 +867,7 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev,
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struct radeon_semaphore *sem = NULL;
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struct radeon_bo_va *bo_va;
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unsigned ngpu_pages, ndw;
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uint64_t pfn;
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uint64_t pfn, addr;
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int r;
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/* nothing to do if vm isn't bound */
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@ -908,21 +892,22 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev,
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ngpu_pages = radeon_bo_ngpu_pages(bo);
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bo_va->flags &= ~RADEON_VM_PAGE_VALID;
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bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM;
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pfn = bo_va->soffset / RADEON_GPU_PAGE_SIZE;
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if (mem) {
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addr = mem->start << PAGE_SHIFT;
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if (mem->mem_type != TTM_PL_SYSTEM) {
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bo_va->flags |= RADEON_VM_PAGE_VALID;
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bo_va->valid = true;
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}
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if (mem->mem_type == TTM_PL_TT) {
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bo_va->flags |= RADEON_VM_PAGE_SYSTEM;
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}
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if (!bo_va->valid) {
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mem = NULL;
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} else {
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addr += rdev->vm_manager.vram_base_offset;
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}
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} else {
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addr = 0;
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bo_va->valid = false;
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}
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pfn = bo_va->soffset / RADEON_GPU_PAGE_SIZE;
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if (vm->fence && radeon_fence_signaled(vm->fence)) {
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radeon_fence_unref(&vm->fence);
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@ -950,7 +935,8 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev,
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radeon_fence_note_sync(vm->fence, ridx);
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}
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radeon_asic_vm_set_page(rdev, vm, pfn, mem, ngpu_pages, bo_va->flags);
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radeon_asic_vm_set_page(rdev, vm->pt_gpu_addr + pfn * 8, addr,
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ngpu_pages, RADEON_GPU_PAGE_SIZE, bo_va->flags);
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radeon_fence_unref(&vm->fence);
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r = radeon_fence_emit(rdev, &vm->fence, ridx);
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